My Inquiry
My Account
Texas Instruments ADS6125IRHBR
- Part No.:
- ADS6125IRHBR
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ADS6125IRHBR.pdf
- Description:
- IC ADC 12BIT PIPELINED 32VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,263
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADS6125IRHBR from Texas Instruments is a 12-bit, 125 MSPS analog-to-digital converter with DDR LVDS or parallel CMOS outputs, internal/external reference support, 3.5 dB coarse + up to 6 dB fine gain programmability, and 32-pin QFN (5 mm × 5 mm) packaging. It delivers 71.1 dBFS SINAD and 78 dBc SFDR at 170 MHz input with 3.5 dB gain, targeting high-speed data acquisition in wireless infrastructure and radar systems.
For engineers reviewing the ADS6125IRHBR datasheet, ADS6125IRHBR pinout, ADS6125IRHBR application, or ADS6125IRHBR equivalent, this page provides verified specifications, validated pin functions, confirmed industrial-temperature (–40°C to 85°C) operation, real-world timing constraints for DDR LVDS capture, and two documented alternative parts within the ADS612X family for sampling-rate-flexible design migration.
Technical Context
The ADS6125IRHBR employs a high-bandwidth sample-and-hold circuit and low-jitter clock buffer to maintain 71.1 dBFS SINAD and 78 dBc SFDR at 170 MHz input frequency. Its dual-output interface supports either DDR LVDS (3.3 V DRVDD, 3.5 mA current, 100 Ω load) or parallel CMOS (1.8–3.3 V DRVDD), with programmable output clock position and drive strength to ease FPGA or ASIC data capture.
Configuration occurs via 3-wire serial interface (SCLK/SEN/SDATA) or dedicated parallel pins (SCLK/SEN/SDATA/PDN) for power-up state control. Internal reference eliminates external decoupling; external reference mode supports 1.45–1.55 V VCM. Clock inputs accept sine, LVCMOS, LVPECL, or LVDS with amplitude down to 400 mVPP and include duty-cycle stabilization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonicity and full code coverage across temperature range. |
| Max Sample Rate | 125 MSPS - enables Nyquist-limited digitization of signals up to 62.5 MHz without aliasing. |
| SINAD @ 170 MHz | 67.6 dBFS (3.5 dB gain) - defines usable dynamic range for wideband RF signal processing. |
| SFDR @ 170 MHz | 78 dBc (3.5 dB gain) - determines spurious-free resolution in dense spectral environments like SDR. |
| Power Consumption | 417 mW total (AVDD + DRVDD) - balances performance and thermal budget in compact 32-QFN layout. |
| Supply Voltages | AVDD = 3.0–3.6 V; DRVDD = 1.8–3.3 V (CMOS) or 3.0–3.6 V (LVDS) - supports mixed-signal voltage domain partitioning. |
| Operating Temperature | –40°C to +85°C - qualified for industrial and outdoor wireless infrastructure deployment. |
| Package | 32-pin QFN (5 mm × 5 mm, RHB designation) - enables high-density PCB routing with thermal pad for thermal management. |
Pinout & Package
ADS6125IRHBR uses a 32-pin QFN package (RHB) with exposed thermal pad. Pin functions are validated per TI SLAS560A datasheet Figures 1–3 and Table 1–3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INP / INM | Differential analog input | Accepts 2 VPP differential signal; 450 MHz analog bandwidth supports IF sampling up to 230 MHz. |
| CLKP / CLKM | Differential clock input | Supports 400 mVPP minimum amplitude; internal duty-cycle stabilizer relaxes clock source requirements. |
| VCM | Common-mode voltage reference | 1.5 V ±0.1 V in internal reference mode; sets input common-mode point for differential pair biasing. |
| CLKOUTP / CLKOUTM | DDR LVDS output clock | Provides synchronized 125 MHz DDR clock for data capture; programmable phase position eases timing closure. |
| D0_D1_P to D10_D11_M | DDR LVDS data pairs (6 pairs) | Transmit 12-bit samples on both clock edges; 225–350 mV differential swing compatible with FPGA LVDS receivers. |
| PDN | Power-down control | Four states: normal, ADC standby, output buffer disable, global power-down - enables dynamic power scaling. |
| SEN / SCLK / SDATA | Serial configuration interface | 3-wire SPI-compatible bus for register programming; also configurable as parallel control pins for boot-time setup. |
| AVDD / AGND / DRVDD / DRGND | Analog/digital supply & ground | Separate analog/digital domains reduce noise coupling; AVDD–DRVDD voltage difference limited to ±0.3 V. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable coarse/fine gain | 3.5 dB coarse + 0–6 dB fine gain improves SFDR at reduced full-scale input (e.g., 1.34 VPP), enabling better dynamic range in low-amplitude signal chains. |
| DDR LVDS or parallel CMOS outputs | Reduces interface pin count by 50% vs. single-data-rate CMOS; DDR LVDS lowers EMI and supports longer trace runs than CMOS at 125 MSPS. |
| Internal reference with no external decoupling | Eliminates two 10 µF reference bypass capacitors, saving board space and simplifying layout while maintaining ±5 mV reference accuracy. |
| Configurable via serial or parallel interface | Parallel pin control (SCLK/SEN/SDATA/PDN) allows deterministic power-up state without firmware initialization; serial interface enables runtime reconfiguration. |
| Clock input flexibility | Accepts sine, LVCMOS, LVPECL, and LVDS clocks with amplitude down to 400 mVPP, reducing need for external level-shifting or amplification circuitry. |
| Output clock position programmability | Adjusts CLKOUT phase relative to data edges to compensate for PCB trace skew and FPGA input delays, easing timing margin validation. |
Applications
| Wireless Communications Infrastructure | Software Defined Radio (SDR) |
|---|---|
|
Use Scenario: Digitizing 20–40 MHz IF signals in LTE base station transceivers with 125 MSPS sampling. IC Role / Device Role / Timing Role: High-speed ADC capturing wideband RF channel data for digital predistortion and MIMO processing. Use Value: 78 dBc SFDR at 170 MHz ensures clean digitization of adjacent channels in crowded spectrum; DDR LVDS interface reduces FPGA I/O count and timing closure risk. |
Use Scenario: Real-time wideband spectrum analysis in field-deployable SDR platforms operating across 100 kHz–2 GHz. IC Role / Device Role / Timing Role: Primary ADC front-end converting antenna signals to baseband IQ samples for FPGA-based FFT and demodulation. Use Value: 12-bit resolution with no missing codes preserves signal fidelity across multi-octave tuning; internal reference eliminates calibration drift in portable units. |
| Power Amplifier Linearization | Radar Systems |
|
Use Scenario: Capturing PA output for digital predistortion (DPD) feedback loop in GaN-based macrocell amplifiers. IC Role / Device Role / Timing Role: High-SFDR ADC sampling PA output at 125 MSPS to extract nonlinear distortion products for adaptive correction. Use Value: 3.5 dB coarse gain extends effective input range to 1.34 VPP, improving SNR for low-level error signal detection without external amplification. |
Use Scenario: Pulse-Doppler radar receiver digitizing 100–200 MHz IF signals in airborne surveillance systems. IC Role / Device Role / Timing Role: High-speed digitizer acquiring chirped radar returns with precise timing alignment for pulse compression and target ranging. Use Value: 1.5 ps rms aperture jitter enables sub-centimeter range resolution; programmable output clock position aligns data capture to FPGA processing pipeline. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS6124IRHBR | 105 MSPS max sample rate; 374 mW power; 82 dBc SFDR @ 170 MHz (3.5 dB gain) | Lower sampling rate suits cost-sensitive 4G small cells or test equipment with <100 MHz bandwidth needs. | Select when system bandwidth ≤52.5 MHz and lower power consumption is prioritized over maximum speed. |
| ADS6123IRHBR | 80 MSPS max sample rate; 318 mW power; 83 dBc SFDR @ 170 MHz (3.5 dB gain); improved SFDR at high frequencies | Better SFDR trade-off for narrowband radar or medical ultrasound where spectral purity outweighs raw speed. | Choose for applications requiring >83 dBc SFDR above 100 MHz with relaxed sampling demands (≤40 MHz Nyquist). |
Compared with ADS6124IRHBR and ADS6123IRHBR, the ADS6125IRHBR delivers highest throughput (125 MSPS) and widest instantaneous bandwidth but at higher power; ADS6124IRHBR offers best balance of speed and efficiency for mid-tier infrastructure, while ADS6123IRHBR prioritizes SFDR integrity in spectrally demanding narrowband systems.
Availability
ADS6125IRHBR is available at Aetrix Electronics and suitable for wireless infrastructure, radar systems, and software-defined radio applications requiring stable component supply, long-term industrial temperature support, and guaranteed QFN-32 sourcing continuity.
Supply support for ADS6125IRHBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance data converters and signal chain solutions.
The ADS612X family-including ADS6125IRHBR-is designed for high-speed digitization in communications, defense, and test equipment, emphasizing low power, flexible interface options, and robust industrial-grade operation.
FAQ
What is the maximum sampling rate supported by the ADS6125IRHBR?
The ADS6125IRHBR supports a maximum sampling rate of 125 MSPS, as specified in the TI SLAS560A datasheet. This rate is fully characterized across the industrial temperature range (–40°C to +85°C) with AVDD = DRVDD = 3.3 V and 50% clock duty cycle. At this rate, the device maintains 71.1 dBFS SINAD and 78 dBc SFDR at 170 MHz input with 3.5 dB coarse gain. The ADS6125IRHBR is the highest-speed variant in the ADS612X family.
Does the ADS6125IRHBR require external reference decoupling capacitors?
No, the ADS6125IRHBR does not require external decoupling capacitors for its internal reference. As confirmed in the TI SLAS560A datasheet Features section and Electrical Characteristics table, the device integrates an internal reference (VREFB = 1 V, VREFT = 2 V) and eliminates traditional reference pins and associated external decoupling. This reduces BOM count and PCB area while maintaining ±5 mV reference voltage accuracy across temperature.
What output interface options does the ADS6125IRHBR support?
The ADS6125IRHBR supports two mutually exclusive digital output interfaces: DDR LVDS and parallel CMOS. DDR LVDS operates with DRVDD = 3.3 V, delivers 225–350 mV differential swing into 100 Ω, and uses six differential pairs (D0_D1_P/M through D10_D11_P/M) plus CLKOUTP/M. Parallel CMOS supports DRVDD = 1.8–3.3 V, provides single-ended logic levels, and uses 12 individual D0–D11 outputs with programmable drive strength. Interface selection is controlled via SEN pin voltage or serial register 0x00.
How is the ADS6125IRHBR configured at power-up?
The ADS6125IRHBR can be configured at power-up using either parallel pin control or serial interface programming. In parallel mode (RESET tied to AVDD), SCLK, SEN, SDATA, and PDN pins act as direct control inputs-setting output format, gain, reference mode, and power state without firmware. In serial mode (RESET pulsed low), the same pins become SCLK/SEN/SDATA for 16-bit register writes. Both methods are validated in TI SLAS560A Section "Device Programming Modes" and Figure 4.
What is the purpose of the coarse and fine gain settings in the ADS6125IRHBR?
The coarse (3.5 dB) and fine (0–6 dB) gain settings in the ADS6125IRHBR optimize SFDR performance at reduced full-scale input ranges. For example, applying 3.5 dB coarse gain lowers the full-scale differential input from 2 VPP to 1.34 VPP, improving SFDR by suppressing amplifier-generated harmonics and intermodulation products. Fine gain further adjusts system gain in 0.5 dB steps to maximize dynamic range without clipping-critical in PA linearization and wideband spectrum analysis where signal amplitude varies significantly.
ADS6125IRHBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 125M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 1.65V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-VQFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS6125IRHBR FAQ
1.How can I place an order for ADS6125IRHBR through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS6125IRHBR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS6125IRHBR reliable?
The price and inventory of ADS6125IRHBR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6125IRHBR is usually 5 days.
3.What payment methods are accepted for ADS6125IRHBR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6125IRHBR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS6125IRHBR?
ADS6125IRHBR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS6125IRHBR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS6125IRHBR?
For technical support, including ADS6125IRHBR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6125IRHBR requirements.
6.How does Aetrix verify that ADS6125IRHBR is sourced from the original manufacturer or authorized distributors?
All ADS6125IRHBR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6125IRHBR meets industry standards.
7.What is the process for return or replacement of ADS6125IRHBR?
All ADS6125IRHBR units undergo pre-shipment inspection (PSI). If there is an issue with ADS6125IRHBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS6125IRHBR part is unused and in its original packaging.
Return procedure for ADS6125IRHBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADS6125IRHBR Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
