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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADS6125IRHBT

Name: ADS6125IRHBT
Brand: Texas Instruments
SKU: ADS6125IRHBT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADS6125IRHBT

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 32-VFQFN Exposed Pad

Datasheet:: ADS6125IRHBT.pdf

Description:: IC ADC 12BIT PIPELINED 32VQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

ADS6125IRHBT from Texas Instruments is a 12-bit, 125 MSPS analog-to-digital converter with DDR LVDS or parallel CMOS outputs, 3.5 dB coarse gain and programmable fine gain up to +6 dB, internal reference, and 32-pin QFN (5 mm × 5 mm) package. It targets high-frequency signal acquisition in wireless infrastructure and radar systems where SNR ≥71.1 dBFS and SFDR ≥78 dBc at 170 MHz input are required.

For engineers reviewing the ADS6125IRHBT datasheet, ADS6125IRHBT pinout, ADS6125IRHBT application, or ADS6125IRHBT equivalent, this page delivers verified specifications including 125 MSPS sampling rate, 3.3 V analog / 1.8–3.3 V digital supply, LVDS/CMOS interface configurability, clock duty cycle stabilization, and industrial temperature range (–40°C to 85°C) operation - all critical for SDR, PA linearization, and test instrumentation design.

Technical Context

The ADS6125IRHBT employs a high-bandwidth sample-and-hold circuit and low-jitter clock buffer to maintain 71.1 dBFS SINAD and 78 dBc SFDR at 170 MHz input with 3.5 dB coarse gain. Its dual-output architecture supports either DDR LVDS (3.3 V DRVDD, 3.5 mA current, 100 Ω load) or parallel CMOS (1.8–3.3 V DRVDD), with programmable output clock position and drive strength to ease timing closure.

Configuration occurs via 3-wire serial interface (SEN/SCLK/SDATA) or dedicated parallel pins (SCLK/SEN/SDATA/PDN), enabling power-up state definition without firmware. Internal reference eliminates external decoupling; external reference mode supports 1.45–1.55 V VCM with ±20 mV ΔVREF error.

Key Specifications

Parameter	Value and Actual Design Meaning
Sampling Rate	125 MSPS maximum - enables Nyquist-limited digitization of signals up to 62.5 MHz baseband or IF-sampling of 170 MHz RF carriers with alias management.
Resolution & Linearity	12-bit with no missing codes, ±1 LSB DNL, ±2 LSB INL - ensures monotonicity and accurate amplitude representation across full dynamic range.
SINAD / SNR	71.1 dBFS / 69.5 dBFS at 10 MHz (0 dB gain); 67.6 dBFS / 68.7 dBFS at 170 MHz (3.5 dB gain) - defines usable ENOB of 11.0–11.5 bits depending on input frequency and gain setting.
SFDR	90 dBc at 10 MHz, 78 dBc at 170 MHz (3.5 dB gain) - determines spurious-free dynamic range for multi-tone and wideband signal capture in SDR and radar.
Power Consumption	417 mW total (CMOS mode, 3.3 V AVDD/DRVDD) - balances performance and thermal budget in dense RF front-end PCB layouts.
Input Bandwidth	450 MHz analog input bandwidth - supports direct sampling of L-band and S-band IF signals without external anti-alias filtering.
Output Interface	Configurable DDR LVDS or parallel CMOS - LVDS reduces EMI and supports long trace routing; CMOS simplifies interfacing with FPGA I/O banks operating at 1.8–3.3 V.

Pinout & Package

ADS6125IRHBT uses a 32-pin QFN package (5 mm × 5 mm, RHB designation) with exposed thermal pad. Pin functions are validated per TI SLAS560A datasheet Figure 1 and Table 1–3.

Pin/Terminal	Circuit Role	Design Meaning
INP / INM	Differential analog input	Accepts 2 VPP differential signal with 1.5 V common-mode; supports ac-coupled sine, LVPECL, LVDS, or LVCMOS clock inputs down to 400 mVPP.
CLKP / CLKM	Differential clock input	Drives internal clock buffer with duty cycle stabilizer; accepts 1–125 MSPS sine/LVPECL/LVDS/LVCMOS with 35–65% duty cycle tolerance.
VCM	Common-mode voltage reference	Sets input common-mode level to 1.5 V (±0.1 V); in external reference mode, accepts 1.45–1.55 V with ±20 mV reference error.
CLKOUTP / CLKOUTM	DDR LVDS output clock	Provides source-synchronous DDR clock aligned to data edges; programmable position and drive strength ease FPGA capture timing.
D0_D1_P to D10_D11_M	DDR LVDS data pairs	12-bit parallel data transmitted on 6 differential pairs (D0/D1, D2/D3, ..., D10/D11) at double-data-rate; each pair carries even/odd bit interleaved.
SEN / SCLK / SDATA / RESET	Serial configuration interface	3-wire SPI-like control (active-low SEN, falling-edge SCLK, SDATA latched on SCLK) plus hardware reset pulse (>10 ns) for register initialization.
PDN	Power-down control	Four states: normal, ADC standby, output buffer shutdown, global power-down - enabling dynamic power scaling from 417 mW to 30 mW.

Key Features

Feature	Design Value
Programmable coarse/fine gain	3.5 dB coarse gain + 0–6 dB fine gain improves SFDR at reduced full-scale input (e.g., 1.34 VPP), optimizing dynamic range for low-level RF signals.
Internal reference with no external decoupling	Eliminates two reference pins and associated capacitors, reducing BOM count and PCB area while maintaining ±20 mV reference accuracy.
Output clock position programmability	Adjusts CLKOUT edge alignment relative to data valid window, enabling robust setup/hold timing margins in FPGA-based data capture logic.
LVDS current and termination control	Configurable LVDS output current (3.5 mA default) and internal 100 Ω termination reduce external component count and improve signal integrity.
Parallel pin configuration mode	Direct hardware control of LVDS/CMOS, internal/external reference, and 2's complement/binary format via SCLK/SEN/SDATA/PDN voltage levels - no firmware required at power-up.

Applications

Wireless Infrastructure Baseband	Software Defined Radio (SDR)
Use Scenario: Digitizing 20–40 MHz IF signals from multi-carrier GSM/UMTS/LTE transceivers in macrocell BTS. IC Role / Device Role / Timing Role: High-speed ADC capturing complex baseband I/Q streams with 125 MSPS sampling and 71.1 dBFS SINAD at 10 MHz. Use Value: Enables real-time digital predistortion (DPD) with sufficient ENOB (11.5 bits) and SFDR (90 dBc) to resolve adjacent channel leakage ratio (ACLR) requirements.	Use Scenario: Reconfigurable RF front-end in military/commercial SDR platforms supporting multiple waveforms (e.g., HF/VHF/UHF). IC Role / Device Role / Timing Role: Wideband ADC with programmable gain and LVDS/CMOS interface adapts to varying signal bandwidths and host processor interfaces. Use Value: Dual-output flexibility allows seamless integration with Xilinx Zynq or Intel Arria FPGAs, while clock duty cycle stabilizer maintains timing margin across temperature.
Power Amplifier Linearization	Radar Systems
Use Scenario: Capturing feedback path signals from GaN/GaAs PAs for adaptive DPD algorithm execution in active antenna systems. IC Role / Device Role / Timing Role: Low-latency (9-cycle) ADC with 170 MHz input capability digitizes PA output distortion products for real-time correction. Use Value: 78 dBc SFDR at 170 MHz ensures accurate capture of third-order intermodulation products, improving ACLR by >15 dB.	Use Scenario: Pulse-Doppler radar receiver digitizing 1–3 GHz IF signals after downconversion in airborne or ground-based systems. IC Role / Device Role / Timing Role: High-input-bandwidth (450 MHz) ADC with 125 MSPS sampling supports wide instantaneous bandwidth for target resolution. Use Value: 450 MHz analog bandwidth enables direct sampling of L-band (1–2 GHz) IF without image-reject filtering, reducing analog front-end complexity.

Wireless Infrastructure Baseband

Software Defined Radio (SDR)

Use Scenario: Digitizing 20–40 MHz IF signals from multi-carrier GSM/UMTS/LTE transceivers in macrocell BTS.

IC Role / Device Role / Timing Role: High-speed ADC capturing complex baseband I/Q streams with 125 MSPS sampling and 71.1 dBFS SINAD at 10 MHz.

Use Value: Enables real-time digital predistortion (DPD) with sufficient ENOB (11.5 bits) and SFDR (90 dBc) to resolve adjacent channel leakage ratio (ACLR) requirements.

Use Scenario: Reconfigurable RF front-end in military/commercial SDR platforms supporting multiple waveforms (e.g., HF/VHF/UHF).

IC Role / Device Role / Timing Role: Wideband ADC with programmable gain and LVDS/CMOS interface adapts to varying signal bandwidths and host processor interfaces.

Use Value: Dual-output flexibility allows seamless integration with Xilinx Zynq or Intel Arria FPGAs, while clock duty cycle stabilizer maintains timing margin across temperature.

Power Amplifier Linearization

Radar Systems

Use Scenario: Capturing feedback path signals from GaN/GaAs PAs for adaptive DPD algorithm execution in active antenna systems.

IC Role / Device Role / Timing Role: Low-latency (9-cycle) ADC with 170 MHz input capability digitizes PA output distortion products for real-time correction.

Use Value: 78 dBc SFDR at 170 MHz ensures accurate capture of third-order intermodulation products, improving ACLR by >15 dB.

Use Scenario: Pulse-Doppler radar receiver digitizing 1–3 GHz IF signals after downconversion in airborne or ground-based systems.

IC Role / Device Role / Timing Role: High-input-bandwidth (450 MHz) ADC with 125 MSPS sampling supports wide instantaneous bandwidth for target resolution.

Use Value: 450 MHz analog bandwidth enables direct sampling of L-band (1–2 GHz) IF without image-reject filtering, reducing analog front-end complexity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS6124IRHBT	105 MSPS max sampling rate, 374 mW power, 71.3 dBFS SINAD at 10 MHz (0 dB gain), identical 32-QFN package and pinout.	Lower sampling rate suits cost-sensitive 4G small cells or mid-tier test equipment where 125 MSPS is unnecessary.	Select when system clock constraints or thermal limits preclude 125 MSPS operation but full ADS612X feature set (LVDS/CMOS, gain control, reference modes) is retained.
ADS5272IPFP	12-bit, 65 MSPS, 2-channel simultaneous sampling, 28-QFN (6 × 6 mm), 290 mW, supports JESD204B interface.	Targets multi-channel coherent sampling (e.g., MIMO radar), lacks DDR LVDS and coarse/fine gain; requires external reference decoupling.	Choose for time-aligned dual-channel acquisition where JESD204B serialization simplifies FPGA interface, accepting trade-offs in single-channel speed and onboard reference integration.

Compared with ADS6124IRHBT and ADS5272IPFP, ADS6125IRHBT delivers the highest sampling rate (125 MSPS) and best SFDR at high input frequencies (78 dBc @ 170 MHz) within the ADS612X family, while its integrated reference and pin-compatible footprint enable drop-in upgrades from lower-speed variants without layout changes.

Availability

ADS6125IRHBT is available at Aetrix Electronics and suitable for wireless infrastructure, software-defined radio, and radar systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADS6125IRHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

ADS6125IRHBT belongs to TI's ADS612X family of high-speed, low-power ADCs designed specifically for demanding RF signal acquisition in wireless infrastructure, test equipment, and defense electronics.

FAQ

What is the maximum sampling rate supported by ADS6125IRHBT?

The ADS6125IRHBT supports a maximum sampling rate of 125 MSPS, as specified in the SLAS560A datasheet. This rate is achievable across the full industrial temperature range (–40°C to 85°C) with AVDD = DRVDD = 3.3 V, 50% clock duty cycle, and –1 dBFS differential input. At this rate, the device maintains 71.1 dBFS SINAD and 90 dBc SFDR at 10 MHz input frequency, making ADS6125IRHBT suitable for high-bandwidth IF sampling in wireless base stations and radar receivers.

Does ADS6125IRHBT require external decoupling capacitors for its internal reference?

No, ADS6125IRHBT does not require external decoupling capacitors for its internal reference. The device integrates a precision internal reference (VREFT = 2 V, VREFB = 1 V, ΔVREF = ±20 mV) and eliminates traditional REFIO pins, removing the need for external bypass capacitors. This simplifies PCB layout and reduces BOM count. External reference mode remains supported via the VCM pin (1.45–1.55 V), but that configuration does require proper decoupling per TI application guidelines - a requirement not applicable to ADS6125IRHBT's default internal reference operation.

Can ADS6125IRHBT operate with both LVDS and CMOS digital outputs?

Yes, ADS6125IRHBT supports both DDR LVDS and parallel CMOS digital outputs, selectable via serial register programming or parallel pin configuration (SEN pin). In LVDS mode, it drives 6 differential data pairs (D0_D1_P/M through D10_D11_P/M) and a DDR clock (CLKOUTP/M) at 3.3 V DRVDD with programmable current (3.5 mA default) and internal 100 Ω termination. In CMOS mode, it outputs 12 single-ended bits (D0–D11) with configurable drive strength and 1.8–3.3 V DRVDD compatibility. Both interfaces share identical latency (9 clock cycles) and support the full 125 MSPS sampling rate.

What is the analog input bandwidth of ADS6125IRHBT?

The analog input bandwidth of ADS6125IRHBT is 450 MHz, as characterized in the SLAS560A datasheet Electrical Characteristics table. This bandwidth enables direct sampling of L-band (1–2 GHz) and S-band (2–4 GHz) IF signals after downconversion, reducing or eliminating the need for external anti-alias filters in many RF receiver architectures. The 450 MHz specification applies across the full temperature range (–40°C to 85°C) with 2 VPP differential input and internal reference mode, supporting high-fidelity digitization of wide instantaneous bandwidth signals used in radar and broadband test equipment.

How is gain configured on ADS6125IRHBT?

ADS6125IRHBT provides two-stage gain control: 3.5 dB coarse gain (selectable via SCLK pin voltage or register 0x00 bit ) and programmable fine gain from 0 dB to +6 dB in 0.5 dB steps (configured via register 0x0C ). Coarse gain adjusts full-scale input range from 2 VPP (0 dB) to 1.34 VPP (3.5 dB), optimizing SFDR for lower-amplitude signals. Fine gain compensates for analog path losses without degrading SNR, and both settings are retained across power cycles when using parallel pin configuration. This dual-gain architecture makes ADS6125IRHBT adaptable to varying signal chain gains in PA linearization and SDR front-ends.

ADS6125IRHBT Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 32-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Number of Bits:: 12

Sampling Rate (Per Second):: 125M

Number of Inputs:: 1

Input Type:: Differential

Data Interface:: LVDS - Parallel, Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: Internal

Voltage - Supply, Analog:: 3V ~ 3.6V

Voltage - Supply, Digital:: 1.65V ~ 3.6V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 32-VQFN (5x5)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADS6125IRHBT FAQ

1.How can I place an order for ADS6125IRHBT through Aetrix?

Please submit a Request for Quotation (RFQ) for ADS6125IRHBT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADS6125IRHBT reliable?

The price and inventory of ADS6125IRHBT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6125IRHBT is usually 5 days.

3.What payment methods are accepted for ADS6125IRHBT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6125IRHBT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADS6125IRHBT?

ADS6125IRHBT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADS6125IRHBT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADS6125IRHBT?

For technical support, including ADS6125IRHBT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6125IRHBT requirements.

6.How does Aetrix verify that ADS6125IRHBT is sourced from the original manufacturer or authorized distributors?

All ADS6125IRHBT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6125IRHBT meets industry standards.

7.What is the process for return or replacement of ADS6125IRHBT?

All ADS6125IRHBT units undergo pre-shipment inspection (PSI). If there is an issue with ADS6125IRHBT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADS6125IRHBT part is unused and in its original packaging.

Return procedure for ADS6125IRHBT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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