Texas Instruments ADS6128IRGZT

Overview

ADS6128IRGZT from Texas Instruments is a 12-bit, 210 MSPS analog-to-digital converter (ADC) with dual DDR LVDS and parallel CMOS digital outputs, 687 mW total power at full rate, internal/external reference support, and DC offset correction - deployed in wireless infrastructure baseband receivers requiring high dynamic range and low latency.

For engineers reviewing the ADS6128IRGZT datasheet, ADS6128IRGZT pinout, ADS6128IRGZT application, or ADS6128IRGZT equivalent, this page delivers verified specifications, validated package mapping, confirmed timing behavior at 210 MSPS, and real-world interface constraints for LVDS/CMOS output modes and clock input amplitude down to 400 mV_PP differential.

Technical Context

The ADS6128IRGZT implements a pipeline ADC architecture with sample-and-hold, on-chip reference generation, and a DDR serializer for LVDS output. It supports programmable fine gain (up to +6 dB) to optimize SFDR vs. SNR trade-offs at reduced input ranges.

Its dual-output interface allows runtime selection between DDR LVDS (100 Ω differential termination) and parallel CMOS (DRVDD-referenced), with configurable data format (2's complement or offset binary) and output clock edge alignment via SEN/DFS pins. Latency is fixed at 18 clock cycles in default mode.

Key Specifications

Pinout & Package

ADS6128IRGZT is housed in a 48-pin QFN package (7 mm × 7 mm, RGZ designation) with exposed thermal pad. Pin functions are validated per TI SLWS211B datasheet Figures 2–4 and Table 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS6129IRGZT and ADS5547IPAP, the ADS6128IRGZT uniquely balances 210 MSPS throughput, 12-bit resolution, DDR LVDS/CMOS flexibility, and 687 mW power - making it the most suitable choice for cost-sensitive, thermally constrained wireless infrastructure designs operating precisely at the 210 MSPS boundary.

Availability

ADS6128IRGZT is available at Aetrix Electronics and suitable for wireless infrastructure baseband receivers, software-defined radio platforms, power amplifier linearization systems, and test & measurement instrumentation requiring stable component supply across extended product lifecycles.

Supply support for ADS6128IRGZT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.

The ADS61xx family was designed specifically for high-speed, wideband communications receivers - emphasizing dynamic performance (SFDR/SNR), flexible digital interfacing, and low-power operation in compact QFN packages for base station and instrumentation applications.

FAQ

What is the maximum analog input frequency supported by the ADS6128IRGZT?

The ADS6128IRGZT supports analog input frequencies up to 500 MHz with a 2 V_PP input amplitude and up to 800 MHz with a 1 V_PP amplitude, as specified in the recommended operating conditions table. Its analog input bandwidth is 700 MHz, ensuring minimal roll-off within these ranges. This capability makes the ADS6128IRGZT suitable for undersampling applications in IF digitization and broadband spectrum analysis.

Does the ADS6128IRGZT require an external reference, or does it include an internal one?

The ADS6128IRGZT includes an internal reference and can operate without any external reference components - eliminating the need for external reference ICs and associated decoupling capacitors. However, it also supports external reference mode via the VREF pin, allowing designers to substitute a higher-accuracy or temperature-stable reference when system-level gain accuracy demands exceed the internal reference's ±1.25% FS specification.

What are the key timing differences between LVDS and CMOS output modes on the ADS6128IRGZT?

In LVDS mode, the ADS6128IRGZT delivers data with 1.0–1.4 ns setup time and 0.4–0.8 ns hold time relative to CLKOUT at 210 MSPS; in CMOS mode, tSTART is 1.7 ns and data valid window is 1.6–2.4 ns. LVDS offers superior noise immunity and timing margin for high-speed FPGA interfaces, while CMOS simplifies board routing at lower speeds but requires stricter load capacitance control (≤5 pF per pin).

How does the DC offset correction function work on the ADS6128IRGZT?

The ADS6128IRGZT integrates a closed-loop DC offset correction circuit that continuously measures and subtracts static offset error from the ADC transfer function. It reduces initial offset from ±15 mV to <±2 mV across temperature and supply variations, with a temperature coefficient of only 0.005 mV/°C. This correction is enabled by default and requires no host processor intervention, making the ADS6128IRGZT ideal for unattended or calibration-free systems.

Is the ADS6128IRGZT pin-compatible with other devices in the ADS61xx family?

Yes - the ADS6128IRGZT shares identical pinout and package (48-QFN RGZ) with ADS6129IRGZT, ADS6148IRGZT, and ADS6149IRGZT. It is also explicitly documented as pin-compatible with the ADS5547 family, enabling layout reuse across multiple generations of TI high-speed ADCs. This compatibility simplifies design migration and reduces PCB redesign risk in platform-based development.