Texas Instruments ADS6143IRHB25

Overview

ADS6143IRHB25 from Texas Instruments is a 14-bit, 80 MSPS analog-to-digital converter with dual-output interface support (DDR LVDS or parallel CMOS), internal reference, and programmable coarse/fine gain. It delivers 74.5 dBFS SINAD at 10 MHz input and 83 dBc SFDR at 170 MHz with 3.5 dB coarse gain, targeting high-fidelity signal acquisition in wireless infrastructure and test instrumentation.

For engineers reviewing the ADS6143IRHB25 datasheet, ADS6143IRHB25 pinout, ADS6143IRHB25 application, or ADS6143IRHB25 equivalent, key selection criteria include sampling rate (80 MSPS), LVDS/CMOS output flexibility, 3.3-V analog / 1.8–3.3-V digital supply compatibility, clock amplitude tolerance down to 400 mV_PP, and industrial temperature range (–40°C to 85°C).

Technical Context

The ADS6143IRHB25 implements a high-bandwidth sample-and-hold with low-jitter clock buffer to maintain SNR/SFDR performance up to 450 MHz analog input bandwidth. Its architecture supports both DDR LVDS (3.3-V DRVDD, 100-Ω differential load) and parallel CMOS (1.8–3.3-V DRVDD) outputs with programmable drive strength and output clock positioning.

Configuration is achieved via either 3-wire serial interface (SEN/SCLK/SDATA) or dedicated parallel pins (SCLK/SEN/PDN) for power-up state control. Internal reference eliminates external decoupling; external reference mode is also supported with VCM = 1.5 V ±0.1 V.

Key Specifications

Pinout & Package

The ADS6143IRHB25 is housed in a 32-pin QFN package (5 mm × 5 mm) with exposed thermal pad, θ_JA = 34 °C/W (0 LFM), and JEDEC-compliant footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS6144IRHB25, the ADS6143IRHB25 trades 25 MSPS throughput for 43 mW lower CMOS-mode power; versus ADS6123IRHB25, it adds 2 bits of resolution and 15 MSPS while increasing power by 33 mW - enabling higher-fidelity digitization where SNR and SFDR are critical.

Availability

ADS6143IRHB25 is available at Aetrix Electronics and suitable for radar systems, wireless communications infrastructure, and test and measurement instrumentation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADS6143IRHB25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.

The ADS614X product line was designed for high-performance, low-power digitization in RF and communications systems - emphasizing flexible interface options, integrated references, and robust AC performance across extended temperature ranges.

FAQ

What is the maximum sampling rate supported by the ADS6143IRHB25?

The ADS6143IRHB25 supports a maximum sampling rate of 80 MSPS. This is confirmed in the device family summary table and electrical characteristics section of the official TI datasheet SLWS198B. At this rate, the ADS6143IRHB25 maintains specified AC performance including 74.5 dBFS SINAD at 10 MHz input and 83 dBc SFDR at 170 MHz with 3.5 dB coarse gain. Sampling above 80 MSPS is not supported and may result in undefined behavior or specification violation.

Does the ADS6143IRHB25 require external decoupling capacitors for its internal reference?

No, the ADS6143IRHB25 does not require external decoupling capacitors for its internal reference. The datasheet explicitly states "No External Decoupling Required for References" under Key Features and confirms this in the APPLICATIONS section. The internal reference (VREFT = 2 V, VREFB = 1 V) is designed for self-contained operation, eliminating the need for external bypassing and reducing PCB area and BOM count. External reference mode remains supported but requires proper VCM biasing per datasheet specifications.

Can the ADS6143IRHB25 operate with a 1.8-V digital supply in LVDS mode?

No, the ADS6143IRHB25 requires a 3.3-V DRVDD supply for LVDS operation. The RECOMMENDED OPERATING CONDITIONS table specifies DRVDD = 3.0–3.6 V for LVDS Interface, and the DIGITAL CHARACTERISTICS section defines LVDS output parameters (e.g., |VOD| = 225–350 mV) only at DRVDD = 3.3 V with IO = 3.5 mA. While 1.8 V is supported for CMOS outputs, using 1.8 V with LVDS will fail to meet LVDS voltage swing and termination requirements, resulting in invalid signaling. The datasheet notes that 1.8 V DRVDD is recommended only for migration to higher-speed next-generation devices.

What clock input types are compatible with the ADS6143IRHB25?

The ADS6143IRHB25 supports sine wave, LVCMOS, LVPECL, and LVDS clock inputs. The datasheet specifies differential clock amplitude requirements: ≥400 mV_PP for sine, ±0.8 V for LVPECL, ±0.35 V for LVDS, and 3.3 V for LVCMOS - all ac-coupled. Clock duty cycle must be between 35% and 65%, and the device includes an on-chip clock duty cycle stabilizer to relax external clock generation requirements. These options provide flexibility in synchronizing the ADS6143IRHB25 with various clock sources across RF, test, and communications platforms.

How is the output interface (LVDS vs. CMOS) configured on the ADS6143IRHB25?

The output interface on the ADS6143IRHB25 is configured using the SEN pin in parallel control mode: SEN = 0 V selects DDR LVDS, (3/8)AVDD selects DDR LVDS with straight binary format, (5/8)AVDD selects parallel CMOS with straight binary, and AVDD selects parallel CMOS with 2's complement. Alternatively, the serial interface (register 0x04, bit ) provides software control. Both methods are mutually exclusive - parallel control takes precedence when RESET is held high, while serial programming requires RESET low. Configuration is latched at power-up or after reset.