My Inquiry
My Account
Texas Instruments ADS6143IRHBT
- Part No.:
- ADS6143IRHBT
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ADS6143IRHBT.pdf
- Description:
- IC ADC 14BIT PIPELINED 32VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,943
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADS6143IRHBT from Texas Instruments is a 14-bit, 80 MSPS analog-to-digital converter with DDR LVDS or parallel CMOS outputs, internal reference, and programmable coarse/fine gain. It delivers 74.5 dBFS SINAD at 10 MHz input and 83 dBc SFDR at 170 MHz with 3.5 dB coarse gain, targeting high-performance data acquisition in radar and SDR systems.
For engineers reviewing the ADS6143IRHBT datasheet, ADS6143IRHBT pinout, ADS6143IRHBT application, or ADS6143IRHBT equivalent, key selection considerations include its 32-pin QFN package, dual-output interface flexibility, clock duty cycle stabilizer, 3.3-V analog / 1.8–3.3-V digital supply support, and industrial temperature range (–40°C to 85°C).
Technical Context
The ADS6143IRHBT implements a high-bandwidth sample-and-hold with low-jitter clock buffer to maintain 74.5 dBFS SINAD up to 170 MHz input frequency. Its architecture supports both internal reference (1 V to 2 V) and external reference modes, eliminating need for external decoupling capacitors on reference pins.
Digital interface configuration is supported via either 3-wire serial interface (SCLK/SEN/SDATA) or dedicated parallel control pins (SCLK/SEN/PDN), enabling flexible power-up state definition without firmware initialization. Output timing includes programmable output clock position and drive strength for reliable DDR LVDS or CMOS capture.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 14-bit with no missing codes - guarantees monotonicity and full code coverage across full dynamic range. |
| Max Sample Rate | 80 MSPS - defines maximum real-time bandwidth for baseband or IF sampling applications. |
| SINAD @ 10 MHz | 74.5 dBFS - determines effective resolution under typical narrowband signal conditions. |
| SFDR @ 170 MHz | 83 dBc (3.5 dB coarse gain) - specifies spurious-free dynamic range for wideband or multi-tone signals. |
| Analog Input BW | 450 MHz - enables direct sampling of IF signals up to ~225 MHz (Nyquist-limited). |
| Power Consumption | 318 mW (CMOS, 3.3 V DRVDD) - sets thermal and board-level power budget for high-density ADC arrays. |
| Supply Voltages | AVDD = 3.0–3.6 V; DRVDD = 1.8–3.3 V (CMOS) or 3.0–3.6 V (LVDS) - supports mixed-voltage system integration. |
| Operating Temp | –40°C to +85°C - qualifies for industrial and outdoor communications infrastructure deployment. |
Pinout & Package
The ADS6143IRHBT is housed in a 32-pin QFN package (5 mm × 5 mm) with exposed thermal pad, θJA = 34 °C/W (0 LFM), and JEDEC-compliant footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INP / INM | Differential analog input | Accepts 2 VPP differential signal with 1.5 V common-mode; supports ac-coupled sine/LVPECL/LVDS clocks. |
| CLKP / CLKM | Differential clock input | Supports 400 mVPP to 1.5 VPP amplitude; integrated duty cycle stabilizer reduces jitter sensitivity. |
| VCM | Common-mode voltage reference | 1.5 V ±0.1 V output for external circuit biasing; used only in external reference mode. |
| D0_D1_P / D0_D1_M through D12_D13_P / D12_D13_M | DDR LVDS data pairs | 7-bit DDR LVDS bus (D0–D13) with 225–350 mV differential swing; supports 100 Ω termination. |
| D0–D13 | Parallel CMOS data outputs | 14-bit CMOS bus with programmable drive strength; compatible with 1.8–3.3 V logic families. |
| CLKOUTP / CLKOUTM | DDR LVDS output clock | Source-synchronous clock for LVDS data capture; 40–55% duty cycle, programmable phase alignment. |
| SCLK / SEN / SDATA / RESET | Serial programming interface | 3-wire SPI-compatible interface for register configuration; RESET initializes internal registers on power-up. |
| PDN | Power-down control | Four states: normal, ADC standby, output buffer disable, global power-down - enables fine-grained power management. |
| AVDD / AGND / DRVDD / DRGND | Analog/digital supplies | Separate analog and digital domains prevent noise coupling; AVDD and DRVDD may be independently regulated. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable coarse/fine gain | 3.5 dB coarse + up to 6 dB fine gain improves SFDR at reduced full-scale input ranges without external amplifiers. |
| Internal reference with no external decoupling | Eliminates four external 10-µF capacitors, reducing BOM count and PCB area in space-constrained designs. |
| DDR LVDS and parallel CMOS output options | Enables migration between low-noise LVDS (318 mW) and FPGA-friendly CMOS (285 mW) without layout change. |
| Integrated clock duty cycle stabilizer | Compensates for >15% input clock duty cycle variation, relaxing requirements on upstream clock generators. |
| Flexible configuration interface | Parallel pin control allows immediate power-up operation; serial interface enables runtime reconfiguration of gain, clock phase, and output format. |
| Industrial temperature range | Validated performance from –40°C to +85°C ensures reliability in base station RF units and test equipment enclosures. |
Applications
| Radar Systems | Software Defined Radio |
|---|---|
Use Scenario: Digitizing IF signals from pulsed Doppler radar receivers operating at 100–200 MHz center frequencies. IC Role / Device Role / Timing Role: High-speed ADC capturing 80 MSPS sampled IF data with 74.5 dBFS SINAD and 83 dBc SFDR at 170 MHz. Use Value: Enables accurate pulse compression and Doppler shift estimation without analog downconversion stages. | Use Scenario: Front-end digitization in multi-band, multi-standard SDR transceivers requiring reconfigurable bandwidth and dynamic range. IC Role / Device Role / Timing Role: 14-bit ADC supporting 80 MSPS sampling with programmable gain and dual LVDS/CMOS interfaces for FPGA interfacing. Use Value: Reduces FPGA I/O count via DDR LVDS and maintains SNR across varying signal amplitudes using coarse/fine gain control. |
| Power Amplifier Linearization | Test and Measurement Instrumentation |
Use Scenario: Capturing feedback signals from wideband GaN power amplifiers for digital predistortion (DPD) algorithms. IC Role / Device Role / Timing Role: ADC acquiring 200+ MHz instantaneous bandwidth signals with 450 MHz analog input bandwidth and low aperture jitter (150 fs rms). Use Value: Improves DPD model accuracy by preserving spectral purity of captured PA output, directly impacting ACLR performance. | Use Scenario: High-fidelity waveform digitization in portable spectrum analyzers and vector signal analyzers. IC Role / Device Role / Timing Role: Precision ADC delivering 74.5 dBFS SINAD and <±2 LSB INL over –40°C to +85°C for calibrated measurement traceability. Use Value: Eliminates need for periodic factory recalibration due to stable DC accuracy and temperature-coefficient performance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS6144IRHBT | 105 MSPS max sample rate; 74.1 dBFS SINAD @ 10 MHz; 374 mW power (CMOS) | Higher throughput for wider IF bandwidths; higher power consumption and cost | Select when >80 MSPS sampling is required and system power budget permits +56 mW increase. |
| ADS6142IRHBT | 65 MSPS max sample rate; 74.6 dBFS SINAD @ 10 MHz; 285 mW power (CMOS) | Lower throughput but lowest power in family; optimized for battery-powered or thermally constrained instruments | Select when 65 MSPS suffices and minimizing power or cost is prioritized over speed. |
Compared with ADS6144IRHBT and ADS6142IRHBT, the ADS6143IRHBT provides optimal balance of speed (80 MSPS), power (318 mW), and AC performance (74.5 dBFS SINAD), making it ideal for mid-tier SDR and radar front-ends where headroom and efficiency must coexist.
Availability
ADS6143IRHBT is available at Aetrix Electronics and suitable for radar systems, software-defined radio platforms, and test instrumentation requiring stable component supply, long-term production continuity, and guaranteed industrial-temperature-grade performance.
Supply support for ADS6143IRHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.
The ADS614X product line was designed specifically for high-speed, high-resolution digitization in demanding RF and communications infrastructure applications, emphasizing low power, flexible interface options, and robust industrial-grade operation.
FAQ
What is the maximum sampling rate supported by the ADS6143IRHBT?
The ADS6143IRHBT supports a maximum sampling rate of 80 MSPS, as specified in the device's recommended operating conditions and electrical characteristics tables. This rate is validated across the full industrial temperature range (–40°C to +85°C) with AVDD = 3.3 V and proper clock signal integrity. The ADS6143IRHBT is the 80 MSPS variant within the ADS614X family, positioned between the 105 MSPS ADS6144IRHBT and 65 MSPS ADS6142IRHBT.
Does the ADS6143IRHBT require external decoupling capacitors on its reference pins?
No, the ADS6143IRHBT does not require external decoupling capacitors on its reference pins. Its internal reference architecture eliminates traditional reference pins and associated external decoupling components, as confirmed in the datasheet's "Features" and "Electrical Characteristics" sections. External reference mode is supported, but even then, no decoupling is mandated per the design specification.
Can the ADS6143IRHBT operate with both LVDS and CMOS digital outputs simultaneously?
No, the ADS6143IRHBT cannot operate with both LVDS and CMOS outputs simultaneously. Output interface selection is mutually exclusive and configured at power-up via the SEN pin (Table 2) or serial register 0x04. In LVDS mode, the Dn_Dn+1_P/M pins drive DDR LVDS pairs; in CMOS mode, D0–D13 drive single-ended CMOS signals. The hardware does not support concurrent activation of both interfaces.
What is the analog input bandwidth of the ADS6143IRHBT, and how does it affect system design?
The ADS6143IRHBT has an analog input bandwidth of 450 MHz, as specified in the Electrical Characteristics table. This enables direct sampling of IF signals up to approximately 225 MHz (half the bandwidth) while maintaining usable SNR and SFDR. System designers must ensure anti-alias filter roll-off begins before 225 MHz and that PCB layout preserves signal integrity through the 450 MHz analog path, including matched differential routing and controlled impedance.
How is gain configured on the ADS6143IRHBT, and what impact does it have on dynamic performance?
The ADS6143IRHBT supports 3.5 dB coarse gain and up to 6 dB programmable fine gain, configured via parallel pins (SCLK/SEN) or serial register 0x0B/0x0C. Applying coarse gain reduces full-scale input range from 2 VPP to 1.34 VPP, improving SFDR at lower input amplitudes - e.g., SFDR increases from 76 dBc to 83 dBc at 170 MHz - without degrading SNR, as verified in the Performance Summary table.
ADS6143IRHBT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 14
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 1.65V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-VQFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS6143IRHBT FAQ
1.How can I place an order for ADS6143IRHBT through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS6143IRHBT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS6143IRHBT reliable?
The price and inventory of ADS6143IRHBT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6143IRHBT is usually 5 days.
3.What payment methods are accepted for ADS6143IRHBT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6143IRHBT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS6143IRHBT?
ADS6143IRHBT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS6143IRHBT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS6143IRHBT?
For technical support, including ADS6143IRHBT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6143IRHBT requirements.
6.How does Aetrix verify that ADS6143IRHBT is sourced from the original manufacturer or authorized distributors?
All ADS6143IRHBT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6143IRHBT meets industry standards.
7.What is the process for return or replacement of ADS6143IRHBT?
All ADS6143IRHBT units undergo pre-shipment inspection (PSI). If there is an issue with ADS6143IRHBT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS6143IRHBT part is unused and in its original packaging.
Return procedure for ADS6143IRHBT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADS6143IRHBT Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
