Texas Instruments ADS6145IRHBT

Overview

ADS6145IRHBT from Texas Instruments is a 14-bit, 125 MSPS analog-to-digital converter with DDR LVDS or parallel CMOS outputs, internal reference, programmable coarse/fine gain, and clock duty cycle stabilizer. It delivers 73.7 dBFS SINAD at 10 MHz input (0 dB gain) and 78 dBc SFDR at 170 MHz (3.5 dB gain), targeting high-speed data acquisition in radar and wireless infrastructure.

For engineers reviewing the ADS6145IRHBT datasheet, ADS6145IRHBT pinout, ADS6145IRHBT application, or ADS6145IRHBT equivalent, key selection criteria include its 125 MSPS sampling rate, 32-pin QFN package, dual-output interface flexibility, low-jitter clock buffer, and industrial temperature range (–40°C to 85°C).

Technical Context

The ADS6145IRHBT employs a high-bandwidth sample-and-hold circuit and low-jitter clock buffer to maintain 73.7 dBFS SINAD and 78 dBc SFDR at 170 MHz input frequency with 3.5 dB coarse gain. Its architecture supports both DDR LVDS (3.3 V DRVDD, 100 Ω load) and parallel CMOS (1.8–3.3 V DRVDD) output modes, with programmable output clock position and drive strength.

Configuration is achieved via 3-wire serial interface (SEN/SCLK/SDATA) or dedicated parallel pins (SCLK/SEN/PDN) for power-up state control. Internal reference eliminates external decoupling; external reference mode is supported with VCM = 1.45–1.55 V. Clock inputs accept sine, LVCMOS, LVPECL, or LVDS with amplitude down to 400 mVPP.

Key Specifications

Pinout & Package

ADS6145IRHBT uses a 32-pin QFN package (RHB designation) with exposed thermal pad. Pin functions are validated per TI SLWS198B datasheet Figure 1 and Table 1–3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS6144IRHBT and ADS5500IPAP, the ADS6145IRHBT uniquely combines 125 MSPS sampling, DDR LVDS output, and internal reference in a 5×5 mm QFN-enabling compact, low-jitter, mixed-signal designs where interface flexibility and thermal efficiency are critical.

Availability

ADS6145IRHBT is available at Aetrix Electronics and suitable for radar systems, wireless communications infrastructure, and test and measurement instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for ADS6145IRHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with emphasis on high-reliability, precision, and energy-efficient design.

The ADS614X family was engineered for high-speed data acquisition in demanding RF and communications systems, prioritizing SNR/SFDR trade-off control, flexible digital interfacing, and simplified power/reference architecture.

FAQ

What is the maximum sampling rate supported by the ADS6145IRHBT?

The ADS6145IRHBT supports a maximum sampling rate of 125 MSPS, as specified across the full industrial temperature range (–40°C to 85°C). This rate is validated with internal reference, 3.3 V AVDD/DRVDD, and 50% clock duty cycle. At this rate, the device achieves 73.7 dBFS SINAD at 10 MHz input and maintains 78 dBc SFDR at 170 MHz with 3.5 dB coarse gain. The ADS6145IRHBT is the highest-speed variant in the ADS614X family.

Does the ADS6145IRHBT require external decoupling capacitors for its internal reference?

No, the ADS6145IRHBT does not require external decoupling capacitors for its internal reference. The device integrates a complete reference system with VREFT = 2 V and VREFB = 1 V, eliminating traditional reference pins and associated bypass components. External reference mode is supported, but only when VCM is biased to 1.45–1.55 V; in that case, external decoupling may be needed per system-level noise requirements-not due to ADS6145IRHBT reference pin limitations.

Can the ADS6145IRHBT operate with a 1.8-V digital supply voltage?

Yes, the ADS6145IRHBT supports 1.8-V digital supply (DRVDD) specifically for CMOS output operation. Per the recommended operating conditions, DRVDD for CMOS interface ranges from 1.65 V to 3.6 V. However, LVDS operation requires DRVDD = 3.0–3.6 V. When using 1.8 V DRVDD in CMOS mode, output drive strength is reduced, and total power drops to ~625 mW (vs. 417 mW at 3.3 V DRVDD); timing margins must be verified per Figure 87 and Table 8 in the datasheet.

How is the ADS6145IRHBT configured for DDR LVDS versus parallel CMOS output?

The ADS6145IRHBT output interface is selected via the SEN pin in parallel configuration mode: SEN = 0 V selects DDR LVDS, while SEN = 5/8 AVDD selects parallel CMOS. In serial mode, register 0x04 bit controls the interface. DDR LVDS uses 7 differential pairs (D0–D13 + CLKOUT), whereas parallel CMOS uses 14 single-ended outputs plus CLKOUT. Output buffer drive strength and clock position are independently programmable in both modes via serial register writes.

What clock input types and amplitudes are compatible with the ADS6145IRHBT?

The ADS6145IRHBT accepts sine wave, LVCMOS, LVPECL, and LVDS clock inputs. Minimum differential amplitude is 400 mVPP for sine, ±0.8 VPP for LVPECL, ±0.35 VPP for LVDS, and 3.3 VPP for LVCMOS-all ac-coupled. The integrated clock duty cycle stabilizer corrects input duty cycle deviations from 35% to 65%, ensuring consistent sampling aperture timing. Clock jitter tolerance is characterized at 150 fs rms, enabling stable operation with low-phase-noise synthesizers.