Texas Instruments ADS61B23EVM

Overview

ADS61B23EVM from Texas Instruments is an evaluation module designed to characterize the ADS61B23 12-bit, 80-MSPS analog-to-digital converter under controlled signal, reference, and supply conditions. It supports parallel CMOS output mode, buffered analog input, and configurable clocking via transformer or CDCP1803 LVDS fanout. The EVM enables SNR/SFDR validation using coherent sampling techniques with a 10-MHz CW tone input and low-phase-noise clock source.

For engineers reviewing the ADS61B23EVM datasheet, ADS61B23EVM pinout, ADS61B23EVM application, or ADS61B23EVM equivalent, this page provides verified hardware configuration options, jumper-defined operational modes (parallel/serial, offset binary/2s complement), ADC SPI control interface details, FPGA interfacing guidance for TSW1100/TSW1200, and physical layout specifications for high-fidelity ADC evaluation.

Technical Context

The ADS61B23EVM implements dual analog input paths: transformer-coupled single-ended input (J8) and THS4509-based differential amplifier path (J10) with selectable dc/ac coupling and gain. Power is supplied via banana jacks J11 (3.3-V digital buffer) and J13 (3.3-V analog), shorted by default via R65. The board integrates a CDCP1803 clock distributor for 1:3 LVDS fanout and supports both transformer-driven and square-wave clock inputs.

ADC interface modes are selected via surface-mount jumpers: JP2–JP4 configure clock path (transformer vs. CDCP1803), JP5–JP6 select analog input path, and JP7 controls THS4509 power state. Digital outputs route to a Samtec QSO-060-01-F-D-A connector (J10), supporting logic analyzer capture, TSW1100/TSW1200 FPGA platforms, or custom digital interface boards.

Key Specifications

Availability

ADS61B23EVM is available at Aetrix Electronics and suitable for high-speed data acquisition systems, precision test equipment, and communications infrastructure requiring stable component supply for ADC performance validation and system-level integration.

Supply support for ADS61B23EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance analog products for industrial, automotive, and communications applications.

The ADS61B23EVM belongs to TI's high-speed ADC evaluation platform family, engineered to accelerate characterization of pipeline ADCs in real-world signal chain environments with flexible clocking, input conditioning, and FPGA interoperability.

FAQ

What is the primary function of the ADS61B23EVM?

The ADS61B23EVM is a dedicated evaluation module for the ADS61B23 12-bit, 80-MSPS analog-to-digital converter. It provides a complete hardware platform-including configurable analog input paths, clock distribution, parallel digital output interface, and SPI control circuitry-to validate ADC performance metrics such as SNR, SFDR, and ENOB under user-defined signal, reference, and supply conditions. ADS61B23EVM enables rapid prototyping and measurement without custom PCB design.

Which ADC models does the ADS61B23EVM support besides the ADS61B23?

The ADS61B23EVM is compatible with the full ADS61xx family including ADS6122, ADS6123, ADS6124, ADS6125, ADS6142, ADS6143, ADS6144, and ADS6145. All share identical pinout, package, and interface architecture with the ADS61B23, allowing the same EVM to evaluate 12- and 14-bit variants across 65–105 MSPS sample rates. ADS61B23EVM jumper configurations and documentation apply uniformly across this group.

How do I configure the ADS61B23EVM for parallel versus serial (SPI) interface mode?

For parallel mode, leave jumper J3 shorted at positions 2–3 (default); for SPI mode, move J3 to positions 1–2. Additional changes are required for SPI: J6 and J7 must be set to 1–2 (USB/FPGA control of SDATA/SCLK), and J2 to 1–2 (USB/FPGA control of SEN). ADS61B23EVM also requires 5 V on J20 to power the USB interface. These settings are documented in Section 3.2 of SLAU206B.

Can the ADS61B23EVM connect directly to Xilinx FPGA development boards?

Yes - the ADS61B23EVM natively interfaces with the TSW1200 FPGA platform via its Samtec connector, and supports the TSW1100 through an optional breakout board. For TSW1200, no adapter is needed; for TSW1100, users must install the provided CMOS breakout board between J2 (Channel 2) and the EVM's J10 connector. ADS61B23EVM jumper settings and firmware updates (e.g., Supported_ADCs.txt) are required for proper FPGA synchronization and data capture.

What clocking options does the ADS61B23EVM provide, and how do they affect ADC performance?

The ADS61B23EVM offers two clock paths: (1) transformer-coupled single-ended input (J9), optimized for low-phase-noise sine-wave sources, and (2) CDCP1803-based LVDS fanout (enabled via JP2–JP4), delivering 1:3 distribution with sub-100-fs jitter contribution in the first Nyquist zone. The CDCP1803 path is unsuitable for high-frequency operation beyond ~40 MHz due to jitter-induced SNR degradation. ADS61B23EVM documentation specifies that transformer path is preferred for full-specification evaluation.