Texas Instruments ADS61B23IRHBR

Overview

ADS61B23IRHBR from Texas Instruments is a 12-bit, 80-MSPS analog-to-digital converter with buffered differential analog inputs, internal reference, and dual-output interface (CMOS or DDR LVDS). It delivers 70 dBFS SNR at –1 dBFS input and 82 dBc SFDR at 10 MHz, operating from 3.3 V analog and 1.8–3.3 V digital supplies in a 32-pin QFN package. It is used in software-defined radio baseband receivers requiring high dynamic range and low input capacitance.

For engineers reviewing the ADS61B23IRHBR datasheet, ADS61B23IRHBR pinout, ADS61B23IRHBR application, or ADS61B23IRHBR equivalent, key selection considerations include its buffered analog input impedance (5 kΩ DC resistance, <2 pF capacitance), programmable coarse/fine gain for SNR/SFDR trade-offs, clock duty cycle stabilizer, and support for both internal and external reference modes - all critical for RF sampling and wideband signal acquisition systems.

Technical Context

The ADS61B23IRHBR employs a switched-capacitor SAR architecture with integrated analog input buffers that isolate external drive circuitry from sampling transients. Its buffered inputs enable stable operation up to >800 MHz analog bandwidth while maintaining <2 pF input capacitance and 5 kΩ DC resistance.

Digital output flexibility is implemented via parallel CMOS or DDR LVDS interfaces, each configurable through serial (3-wire SPI) or parallel control pins. Gain control includes 3.5 dB coarse step and 0–6 dB fine programmability; clock interface supports sine, LVCMOS, LVPECL, and LVDS inputs down to 400 mV_PP, with an on-chip duty cycle stabilizer.

Key Specifications

Pinout & Package

ADS61B23IRHBR is housed in a 32-pin QFN package (5 mm × 5 mm) with exposed thermal pad. Pin functions are defined per TI SLAS582 datasheet Rev F (2008), with dedicated analog, digital, clock, and control terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS61B23IRHBR, ADS61B29IRHBR offers higher speed but sacrifices input buffering and SNR, while ADS41B29IRGZT trades package compatibility and simplicity for raw throughput and modern serial interface - making ADS61B23IRHBR optimal for cost-sensitive, wideband, buffer-critical designs.

Availability

ADS61B23IRHBR is available at Aetrix Electronics and suitable for wireless infrastructure, software-defined radio, and radar systems requiring stable component supply, long-term obsolescence management, and traceable sourcing.

Supply support for ADS61B23IRHBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS61B23IRHBR belongs to TI's ADS61x2x family of high-speed, low-power ADCs designed specifically for wideband communication receivers, test equipment, and instrumentation demanding excellent SFDR and flexible interface options.

FAQ

What is the maximum sampling rate supported by the ADS61B23IRHBR?

The ADS61B23IRHBR supports a maximum sampling rate of 80 MSPS, validated across the full operating temperature range (–40°C to +85°C) with AVDD = 3.3 V and internal reference mode. This rate enables Nyquist sampling of signals up to 40 MHz or undersampling of higher IF frequencies in communications systems.

Does the ADS61B23IRHBR require external reference decoupling capacitors?

No, the ADS61B23IRHBR eliminates external decoupling for its internal reference - a key design feature confirmed in the SLAS582 datasheet. When using internal reference mode, no external capacitors are needed on VREFB/VREFT pins, reducing BOM count and PCB area. External reference mode remains supported if system-level voltage scaling is required.

How does the buffered analog input of the ADS61B23IRHBR improve system design?

The ADS61B23IRHBR's buffered analog inputs present <2 pF capacitance and 5 kΩ DC resistance, isolating the internal sampling switch from external drive circuitry. This reduces sensitivity to PCB trace inductance and eliminates need for complex RC snubbers - enabling direct connection to baluns or wideband amplifiers in SDR and radar front-ends.

Can the ADS61B23IRHBR operate with both CMOS and LVDS digital outputs simultaneously?

No, the ADS61B23IRHBR supports either parallel CMOS or DDR LVDS output mode - not both simultaneously. The interface type is selected at power-up via the SEN pin (Table 3) or programmed via register 0x00 bit D8 (). Output configuration is mutually exclusive and must be fixed per application requirements.

What is the latency of the ADS61B23IRHBR, and how is it affected by output interface choice?

The ADS61B23IRHBR has a fixed latency of 9 clock cycles in both CMOS and DDR LVDS modes, as specified in Figure 1 of the SLAS582 datasheet. This deterministic latency is independent of gain setting, reference mode, or output drive strength - enabling predictable timing alignment in closed-loop systems such as digital predistortion engines.