Texas Instruments ADS61B23IRHBT

Overview

ADS61B23IRHBT from Texas Instruments is a 12-bit, 80-MSPS analog-to-digital converter (ADC) with buffered differential analog inputs, internal reference, and dual-output interface support (CMOS or DDR LVDS). It delivers 70 dBFS SNR and 82 dBc SFDR at –1 dBFS input, operates from 3.3 V analog and 1.8–3.3 V digital supplies, and targets high-frequency signal acquisition in wireless infrastructure and test equipment.

For engineers reviewing the ADS61B23IRHBT datasheet, ADS61B23IRHBT pinout, ADS61B23IRHBT application, or ADS61B23IRHBT equivalent, this page provides verified technical context, real-world timing behavior, gain-programmable SNR/SFDR trade-off control, buffered input drive advantages, and validated alternative options for RF sampling systems requiring low-input-capacitance ADCs.

Technical Context

The ADS61B23IRHBT employs a switched-capacitor SAR architecture with integrated input buffers that present <2 pF capacitance and 5 kΩ DC resistance-enabling direct drive from wideband amplifiers without external isolation networks. Its analog front-end supports up to 800 MHz small-signal bandwidth and features a clock duty cycle stabilizer to maintain timing integrity under asymmetric clock inputs.

Digital output flexibility includes parallel CMOS (12-bit, single-data-rate) or DDR LVDS (6-bit pairs per clock edge), both programmable via 3-wire serial interface or dedicated parallel pins. Gain control combines fixed 3.5 dB coarse step and fine-grained 0–6 dB adjustment (in 1 dB steps), directly trading SNR for SFDR across input frequencies from 10 MHz to 130 MHz.

Key Specifications

Pinout & Package

ADS61B23IRHBT is housed in a 32-pin QFN package (5 mm × 5 mm) with exposed thermal pad, rated for –40°C to +85°C operation. Pin functions are defined per TI SLAS582 datasheet Rev F (2008).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS61B23IRHBT, ADS6142IRHBT trades 15 MSPS speed for +2-bit resolution and maintains pin compatibility, while ADS62P49IRGCT offers dual-channel 250 MSPS operation at the cost of increased power, larger footprint, and loss of integrated reference simplicity.

Availability

ADS61B23IRHBT is available at Aetrix Electronics and suitable for wireless infrastructure, software-defined radio, and test instrumentation applications requiring stable component supply, long-term lifecycle support, and traceable sourcing for production programs.

Supply support for ADS61B23IRHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS61B23IRHBT belongs to TI's ADS61xx family of high-speed, low-power ADCs designed specifically for RF sampling in wireless infrastructure, radar, and instrumentation-emphasizing buffered inputs, flexible output interfaces, and simplified reference architecture.

FAQ

What is the maximum input frequency supported by the ADS61B23IRHBT analog front-end?

The ADS61B23IRHBT specifies an analog input bandwidth of >800 MHz, enabling direct sampling of RF signals up to S-band frequencies. This performance is achieved through its buffered input architecture, which maintains signal integrity without external matching networks. The device achieves 70 dBFS SNR and 78 dBc SFDR at 50 MHz input, confirming usability well into UHF bands. Performance degrades gradually above 100 MHz but remains functional for undersampling applications.

Does the ADS61B23IRHBT require external reference decoupling capacitors?

No, the ADS61B23IRHBT eliminates external decoupling for references by integrating a stable internal reference (1 V bottom / 2 V top) and removing dedicated VREF pins. This reduces BOM count and PCB area while improving noise immunity in RF-sensitive layouts. External reference mode is supported via VCM pin, but even then, no decoupling caps are required-only a clean 1.5 V bias source.

How does the coarse and fine gain control affect SFDR and SNR in the ADS61B23IRHBT?

The ADS61B23IRHBT provides 3.5 dB coarse gain and 0–6 dB fine gain (1 dB steps) to adjust full-scale input range. At –1 dBFS input, 0 dB gain yields 70 dBFS SNR and 82 dBc SFDR; applying 3.5 dB coarse gain shifts optimal operation to –4.5 dBFS, increasing SFDR to 87 dBc at the expense of ~1.3 dB SNR. Fine gain allows precise optimization per signal condition without changing hardware.

What is the latency of the ADS61B23IRHBT, and is it deterministic?

The ADS61B23IRHBT has a fixed 9-clock-cycle latency from analog input sampling to valid digital output, confirmed across temperature and supply variations. This deterministic pipeline delay is critical for real-time applications like digital predistortion (DPD), where feedback loop timing must be precisely known. Latency remains constant regardless of output interface (CMOS or DDR LVDS) or gain setting.

Can the ADS61B23IRHBT operate with a 1.8 V digital supply while using DDR LVDS outputs?

No-DDR LVDS operation requires DRVDD = 3.0–3.6 V per TI SLAS582 specifications. The ADS61B23IRHBT supports 1.8 V digital supply only in CMOS output mode. Attempting DDR LVDS at 1.8 V violates output voltage compliance (LVDS differential swing requires ≥225 mV), risking data corruption. For low-voltage systems, use CMOS mode with DRVDD = 1.8 V or upgrade to 3.3 V for LVDS capability.