Texas Instruments ADS61B29IRGZR

Overview

ADS61B29IRGZR from Texas Instruments is a 12-bit, 250MSPS analog-to-digital converter with integrated high-impedance analog input buffer, DDR LVDS/parallel CMOS outputs, and programmable fine gain up to 6dB. It operates from 3.3V analog and 1.8V digital supplies, dissipates 790mW at full rate, and targets wide-bandwidth communications infrastructure requiring stable DC offset correction and 1Vpp full-scale operation.

For engineers reviewing the ADS61B29IRGZR datasheet, ADS61B29IRGZR pinout, ADS61B29IRGZR application, or ADS61B29IRGZR equivalent, this page delivers verified electrical characteristics (SNR = 70.1 dBFS @ 170MHz), interface timing (LVDS setup/hold: 0.8–1.2 ns / 0.25–0.6 ns), thermal performance (–40°C to 85°C), and pin-compatible migration path from ADS6149 family.

Technical Context

The ADS61B29IRGZR implements a pipelined ADC architecture with on-chip analog buffer enabling constant 10 kΩ differential input impedance and 750 MHz analog bandwidth across 20–300 MHz input frequencies. Its dual-output interface supports DDR LVDS (12-bit data multiplexed on D0_D1_P/M through D10_D11_P/M) or parallel CMOS (D0–D11), selectable via DFS pin.

DC offset correction is implemented as a closed-loop digital calibration circuit, while fine gain adjustment modifies internal reference scaling to trade SNR for SFDR-e.g., +6dB gain improves SFDR by ~3 dBc at 100MHz but reduces SNR by ~1.5 dBFS. Internal references eliminate external decoupling capacitors on VCM and REF pins.

Key Specifications

Pinout & Package

ADS61B29IRGZR uses a 48-pin QFN package (RGZ) with 7.0 mm × 7.0 mm footprint and exposed thermal pad connected to DRGND. Pin functions are mode-dependent: LVDS mode uses differential data pairs (e.g., D0_D1_P/M), while CMOS mode uses single-ended D0–D11 outputs. All power/ground pins are segregated (AVDD/AGND for analog, DRVDD/DRGND for digital), and MODE pin is no-connect.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS6149IRGZR, ADS61B29IRGZR trades 2 bits of resolution for integrated buffering and 130 mW lower power-making it superior for wideband communications where input drive complexity and thermal management dominate. Against AD9629BCPZ-125, its 2× sampling rate and buffer enable direct RF sampling in next-gen wireless infrastructure.

Availability

ADS61B29IRGZR is available at Aetrix Electronics and suitable for wireless infrastructure base stations, software-defined radio platforms, and radar digitizers requiring stable component supply, long-term industrial temperature support (–40°C to 85°C), and guaranteed traceability.

Supply support for ADS61B29IRGZR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance data converters and signal chain solutions.

The ADS61B29IRGZR belongs to TI's ADS61Bx9 family of high-speed ADCs designed specifically for wideband communications infrastructure-emphasizing integrated analog buffering, low-jitter sampling, and flexible digital interfaces to simplify RF receiver design.

FAQ

What is the maximum analog input frequency supported by ADS61B29IRGZR?

The ADS61B29IRGZR supports up to 500 MHz analog input frequency with 2 Vpp differential input amplitude, and extends to 800 MHz at 1 Vpp full-scale operation-enabled by its 750 MHz analog input bandwidth and integrated buffer maintaining flat impedance response.

Does ADS61B29IRGZR require external reference components?

No, ADS61B29IRGZR includes internal references and eliminates traditional REF/REFTN pins and associated decoupling capacitors. The VCM pin serves as common-mode voltage output (2.3 V) in internal reference mode, simplifying layout and reducing BOM count.

How does the fine gain feature affect ADS61B29IRGZR performance?

The programmable fine gain (up to +6 dB) scales the ADC's full-scale range from 1 Vpp to 2 Vpp, improving SFDR by ~3 dBc at 100 MHz while reducing SNR by ~1.5 dBFS-allowing system-level trade-off between spurious-free dynamic range and noise floor based on signal statistics.

What is the ADC latency of ADS61B29IRGZR in LVDS mode?

ADS61B29IRGZR has a fixed 18-clock-cycle latency in LVDS mode after reset, measured from input clock edge to first valid DDR LVDS data pair. This latency remains constant across sampling rates and is critical for deterministic timing in DPD and beamforming applications.

Is ADS61B29IRGZR pin-compatible with other devices in the ADS61x9 family?

Yes, ADS61B29IRGZR is pin-compatible with the ADS6149 family (e.g., ADS6149IRGZR) in the same RGZ-48 package-enabling drop-in replacement for resolution upgrades or buffer removal, provided system firmware accounts for differing register maps and power sequencing.