Texas Instruments ADS61JB46EVM

Overview

ADS61JB46EVM from Texas Instruments is an evaluation module designed to assess the ADS61JB46, a 14-bit, 160 Msps analog-to-digital converter with JESD204B serial output (up to 3.125 Gbps). It integrates an FPGA for JESD204B deserialization and LVDS DDR reformatting, enabling direct interface with TSW1200/TSW1400 capture cards. The board supports single-ended or differential analog input via SMA, transformer-coupled signal conditioning, and configurable power delivery from 5 V or 6–36 V input.

For engineers reviewing the ADS61JB46EVM datasheet, ADS61JB46EVM pinout, ADS61JB46EVM application, or ADS61JB46EVM equivalent, this page delivers verified technical context, key specifications, supply chain availability, manufacturer background, and targeted FAQs - all grounded in TI's SLAU449A User's Guide and official EVM documentation.

Technical Context

The ADS61JB46EVM implements a full signal chain: analog input passes through a dual-transformer differential balun before reaching the ADS61JB46 ADC; clock input is similarly transformer-coupled to generate clean differential sampling clocks. Power is derived from a single 5-V banana jack or a 6–36 V DC-DC input, with onboard LDOs (TPS79601, TPS73225) and switching regulators (PTH03000W, TPS5420D) generating 1.2 V (FPGA), 1.8 V (ADC AVDD/DVDD), 2.5 V (FPGA), and 3.3 V (input buffer).

Signal integrity is maintained via configurable CML termination options (DC- or AC-coupled), zero-Ω surface-mount jumpers for SPI routing (USB vs. TSW1200), and FPGA-controlled synchronization (SYNC assertion, receiver reset via SW3/SW4). The FPGA bridges JESD204B serial data to LVDS DDR parallel format compatible with legacy capture hardware.

Key Specifications

Availability

ADS61JB46EVM is available at Aetrix Electronics and suitable for high-speed data acquisition, RF receiver prototyping, and ADC performance validation requiring stable component supply, traceable sourcing, and long-term lifecycle support.

Supply support for ADS61JB46EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog, embedded processing, and high-performance analog products for industrial, automotive, and communications applications.

The ADS61JBxx EVM product line is part of TI's high-speed data converter evaluation ecosystem, engineered specifically to accelerate characterization and integration of JESD204B-capable ADCs like the ADS61JB46 into demanding signal chain designs.

FAQ

What is the primary function of the ADS61JB46EVM?

The ADS61JB46EVM is an evaluation module built to characterize the ADS61JB46 14-bit, 160 Msps analog-to-digital converter. It provides signal conditioning (transformer-coupled analog input), clock distribution, power regulation, FPGA-based JESD204B deserialization, and LVDS DDR reformatting to interface directly with TI's TSW1200 or TSW1400 capture cards. Its design enables accurate SNR, SFDR, and FFT-based performance analysis without custom hardware development.

Does the ADS61JB46EVM support both single-ended and differential analog inputs?

Yes, the ADS61JB46EVM supports both configurations. By default, the SMA analog input (J4) connects to a transformer primary; installing jumper R77 enables differential mode by connecting the transformer's negative side to the signal path, while installing R78 grounds that side for single-ended operation. This flexibility allows users to evaluate the ADS61JB46 under real-world signal source conditions without modifying the PCB layout.

How does the ADS61JB46EVM handle JESD204B serial data for compatibility with older capture hardware?

The ADS61JB46EVM uses an onboard FPGA to deserialize the JESD204B-encoded serial stream from the ADS61JB46 and convert it into LVDS DDR parallel format. Since the TSW1200 lacks native JESD204B support, this FPGA bridge ensures seamless data capture - preserving timing alignment, frame boundaries, and sample integrity while maintaining backward compatibility with TI's established evaluation infrastructure.

What power supply options are available on the ADS61JB46EVM?

The ADS61JB46EVM accepts either 5 V directly via banana jack J10 or a higher 6–36 V input routed through an onboard TPS5420D DC-DC switcher to generate 5.3 V, followed by a TPS79501 LDO for clean 5 V. From there, dedicated LDOs (TPS79601, TPS73225) and a switching regulator (PTH03000W) produce 1.2 V (FPGA), 1.8 V (ADS61JB46 AVDD/DVDD), 2.5 V (FPGA), and 3.3 V (input buffer), all configurable via jumpers JP15–JP21 per the SLAU449A guide.

Why are pushbuttons SW3 and SW4 required after every power cycle or clock disruption on the ADS61JB46EVM?

SW3 resets the FPGA's JESD204B serial receivers, which lose lock upon clock loss or power interruption; SW4 then asserts the SYNC signal to the ADS61JB46, triggering transmission of a synchronization pattern that enables byte- and frame-alignment recovery in the FPGA. Per SLAU449A Section 1.3, this two-step sequence is mandatory to reestablish valid data flow - skipping either step results in misaligned or corrupted samples during capture.