Texas Instruments ADS6222IRGZ25

Overview

ADS6222IRGZ25 from Texas Instruments is a dual-channel, 12-bit, 65 MSPS analog-to-digital converter with serial LVDS interface, internal reference, 3.5 dB coarse gain, and 48-pin QFN (7 mm × 7 mm) package. It delivers 71.3 dBFS SINAD at 10 MHz input, 83 dBc SFDR at 170 MHz with 3.5 dB gain, and 68.7 dBFS SINAD at 170 MHz - optimized for IF sampling in base-station receivers and medical imaging systems.

For engineers reviewing the ADS6222IRGZ25 datasheet, ADS6222IRGZ25 pinout, ADS6222IRGZ25 application, or ADS6222IRGZ25 equivalent, key selection criteria include its 65 MSPS sample rate, LVDS 2-wire DDR serialization (≤1 Gbps), programmable fine gain (±6 dB in 1-dB steps), industrial temperature range (–40°C to 85°C), and support for internal/external reference modes.

Technical Context

The ADS6222IRGZ25 employs simultaneous sample-and-hold across two independent ADC channels, with an integrated PLL that multiplies the input clock to generate bit and frame clocks for LVDS serialization. Its digital encoder supports both 1-wire and 2-wire LVDS interfaces, where the 2-wire mode halves data rate versus 1-wire by using two differential pairs per channel.

Configuration is supported via parallel pin control (CFG1–CFG4, PDNA/PDNB, SEN) or SPI-compatible serial interface (SEN/SCLK/SDATA), with priority arbitration between modes. Output formatting options include MSB/LSB first and 2's complement/offset binary, while LVDS drivers offer programmable current, current doubling, and internal termination for signal integrity optimization.

Key Specifications

Pinout & Package

ADS6222IRGZ25 is housed in a thermally enhanced 48-pin QFN package (7 mm × 7 mm, RGZ designation) with exposed thermal pad. Pin functions are validated per TI SLAS543B Rev. January 2014.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel ADC applications.

Compared with ADS6223IRGZT and ADS6224IRGZR, the ADS6222IRGZ25 offers the lowest power (315 mW/channel) and tightest thermal envelope for space-constrained IF receivers, trading sample rate for efficiency without sacrificing SINAD or SFDR at its target 65 MSPS operating point.

Availability

ADS6222IRGZ25 is available at Aetrix Electronics and suitable for base-station IF receivers, medical ultrasound systems, and automated test equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADS6222IRGZ25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of innovation in data converters and signal chain solutions.

The ADS622X family was designed for high-density, high-performance communications infrastructure - delivering dual-channel ADC functionality in compact QFN packages with LVDS serialization to reduce FPGA interface complexity and PCB layer count.

FAQ

What is the maximum sampling frequency supported by the ADS6222IRGZ25?

The ADS6222IRGZ25 supports a maximum sampling frequency of 65 MSPS, as specified in the SLAS543B datasheet. This rate is fixed per device variant within the ADS622X family and cannot be increased via configuration. At 65 MSPS, the ADS6222IRGZ25 achieves 71.3 dBFS SINAD at 10 MHz input and 83 dBc SFDR at 170 MHz with 3.5 dB coarse gain - making it ideal for IF sampling in cost- and power-sensitive wireless infrastructure applications.

Does the ADS6222IRGZ25 support both internal and external reference modes?

Yes, the ADS6222IRGZ25 supports both internal and external reference modes. In internal mode, it uses on-chip 1.0 V and 2.0 V references (ΔVREF = 1.0 V ±2 mV) with no external decoupling required. In external mode, it accepts a precision 1.5 V ±5 mV reference applied to VCM, allowing calibration-grade accuracy. The mode is selected via the SEN pin voltage level per Table 6 of the datasheet - a key differentiator from fixed-reference ADCs.

How many LVDS data lanes does the ADS6222IRGZ25 use in 2-wire interface mode?

In 2-wire LVDS interface mode, the ADS6222IRGZ25 uses four differential LVDS lanes: DA0_P/DA0_M and DA1_P/DA1_M for Channel A, and DB0_P/DB0_M and DB1_P/DB1_M for Channel B. Each pair carries serialized 12-bit data at half the sample rate (32.5 MHz bit clock), limiting maximum data rate to <1 Gbps per lane - significantly easing FPGA receiver design compared to parallel or 1-wire LVDS alternatives.

What is the channel-to-channel delay variation specification for the ADS6222IRGZ25?

The ADS6222IRGZ25 specifies a channel-to-channel delay variation of ±80 ps across temperature (–40°C to 85°C), as documented in the "Aperture delay variation" parameter under Timing Specifications. This tight matching ensures phase coherence between dual channels - essential for I/Q demodulation, beamforming, and time-of-flight measurements. The value is measured at the analog input pins and includes internal propagation differences in the SHA and clock distribution networks.

Can the ADS6222IRGZ25 be configured without firmware using only hardware pins?

Yes, the ADS6222IRGZ25 supports full hardware-based configuration via parallel control pins (CFG1–CFG4, PDNA, PDNB, SEN). These pins accept resistor-divider voltages to set interface mode (1-/2-wire), serialization ratio (12x/14x), data format (MSB/LSB, 2's complement/offset binary), coarse gain, and reference source - all without serial programming. This enables immediate operation after power-up, critical for systems lacking boot firmware or requiring fail-safe initialization.