Texas Instruments ADS6223IRGZ25

Overview

ADS6223IRGZ25 from Texas Instruments is a dual-channel, 12-bit, 80 MSPS analog-to-digital converter with serial LVDS interface, simultaneous sample-and-hold architecture, 3.5 dB coarse gain, and internal reference. It operates from 3.3-V analog and digital supplies, delivers 71.3 dBFS SINAD at 10 MHz input (0 dB gain), and targets IF sampling in base-station receivers.

For engineers reviewing the ADS6223IRGZ25 datasheet, ADS6223IRGZ25 pinout, ADS6223IRGZ25 application, or ADS6223IRGZ25 equivalent, key selection factors include its 80 MSPS sampling rate, 2-wire DDR LVDS serialization (≤800 Mbps per channel), programmable fine gain (±6 dB in 1-dB steps), industrial temperature range (–40°C to 85°C), and QFN-48 (7 mm × 7 mm) package with internal termination support.

Technical Context

The ADS6223IRGZ25 implements a pipelined ADC architecture with simultaneous sampling across two independent channels, each featuring a dedicated sample-and-hold amplifier. Its internal PLL multiplies the input clock to generate the bit clock for LVDS serialization, supporting both 1-wire and 2-wire interface modes.

It provides configurable data formatting (MSB/LSB first, 2's complement/offset binary), programmable LVDS output current and internal termination, and three power-down modes-global, per-channel (PDNA/PDNB), and standby-with wake-up times under 200 µs. The device accepts differential analog inputs up to 2 Vpp and supports sine, LVCMOS, LVPECL, or LVDS clock inputs down to 400 mVpp.

Key Specifications

Pinout & Package

ADS6223IRGZ25 is housed in a 48-pin QFN package (7 mm × 7 mm) with exposed thermal pad, θJA = 23.17 °C/W (0 LFM), and RoHS-compliant lead finish.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, LVDS-output ADC applications.

Compared with ADS6224IRGZT and ADS62P23IRGZT, the ADS6223IRGZ25 provides optimal balance of power efficiency (350 mW/channel), proven stability in production, and sufficient dynamic range for 80-MSPS IF sampling-making it ideal for cost- and thermal-sensitive infrastructure deployments.

Availability

ADS6223IRGZ25 is available at Aetrix Electronics and suitable for base-station IF receivers, medical ultrasound front-ends, and automated test equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for ADS6223IRGZ25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, communications, and medical markets.

The ADS622X family-including ADS6223IRGZ25-is designed for high-density, high-performance IF digitization in communications infrastructure, where dual-channel synchronization, LVDS interface scalability, and low-power operation are critical.

FAQ

What is the maximum sampling rate supported by the ADS6223IRGZ25?

The ADS6223IRGZ25 supports a maximum sampling rate of 80 MSPS, as specified across the full industrial temperature range (–40°C to 85°C). This rate is validated with internal reference, 3.3-V supplies, and proper clock conditioning. At this rate, the device maintains 71.3 dBFS SINAD and 82 dBc SFDR at 170 MHz input with 3.5 dB coarse gain, making ADS6223IRGZ25 suitable for wideband IF sampling in base-station and test applications.

Does the ADS6223IRGZ25 support external reference operation?

Yes, the ADS6223IRGZ25 supports both internal and external reference modes. When configured via the SEN pin or register bit D6 of register 0x00, it accepts an external reference applied differentially across REFP and REFM pins. In external mode, the input full-scale range remains 2 Vpp, and VCM must be set to 1.45–1.55 V. This flexibility allows ADS6223IRGZ25 to integrate into systems requiring tighter reference accuracy or custom scaling not achievable with the internal 2.0-V reference.

How does the 2-wire LVDS interface of the ADS6223IRGZ25 reduce system complexity?

The 2-wire LVDS interface of the ADS6223IRGZ25 uses four differential pairs (DA0/DA1 for Channel A, DB0/DB1 for Channel B) to serialize 12-bit data per channel, halving the data rate versus a 1-wire implementation. This reduces FPGA pin count, simplifies PCB routing, and eases timing closure - especially critical for high-speed capture. With DDR clocking, ADS6223IRGZ25 achieves ≤800 Mbps per LVDS lane at 80 MSPS, enabling reliable reception on standard FPGA I/O banks without requiring specialized high-speed transceivers.

What power-down options are available on the ADS6223IRGZ25?

The ADS6223IRGZ25 offers three hardware-controlled power-down modes: global (via SCLK/SDATA command or PDN pin), per-channel (via PDNA and PDNB pins), and standby (via register control). Global power-down cuts total supply current to 77 mW and disables all circuitry including PLL and references. Per-channel mode shuts down only one ADC core while preserving the other's operation - useful in diversity receivers. Standby mode retains configuration and reference bias, enabling wake-up in <200 µs. All modes are accessible without firmware intervention, enhancing ADS6223IRGZ25's suitability for adaptive power management.

Can the ADS6223IRGZ25 be configured using only hardware pins, without serial programming?

Yes, the ADS6223IRGZ25 supports full configuration via parallel interface pins (CFG1–CFG4, SEN, PDNA, PDNB) after power-up, eliminating the need for serial register writes. Resistor-divider networks on CFG pins set interface mode (1-/2-wire), serialization ratio (12x/14x), and data format (MSB/LSB, 2's complement/offset binary); SEN selects reference and coarse gain; PDNA/PDNB control per-channel power state. This hardware-only setup enables rapid, deterministic initialization - a key advantage for ADS6223IRGZ25 in boot-critical or resource-constrained embedded systems.