Texas Instruments ADS6223IRGZT

Overview

ADS6223IRGZT from Texas Instruments is a dual-channel, 12-bit, 80 MSPS analog-to-digital converter with serial LVDS interface, simultaneous sample-and-hold architecture, 3.5 dB coarse gain, and internal reference. It delivers 71.3 dBFS SINAD at 10 MHz input (0 dB gain) and 82 dBc SFDR at 170 MHz (3.5 dB gain), targeting high-density IF sampling in base-station receivers.

For engineers reviewing the ADS6223IRGZT datasheet, ADS6223IRGZT pinout, ADS6223IRGZT application, or ADS6223IRGZT equivalent, this page provides verified specifications, QFN-48 package layout, real-world timing behavior, and validated alternative options for dual-channel 12-bit ADC selection in RF receiver signal chains.

Technical Context

The ADS6223IRGZT implements a two-stage pipeline ADC architecture with integrated digital encoder and serializer. Its internal PLL multiplies the input sampling clock to generate the LVDS bit clock, enabling DDR serialization at 2-wire LVDS mode with 14× oversampling - reducing output data rate to <1 Gbps while maintaining timing integrity.

It supports both 1-wire and 2-wire LVDS output interfaces, programmable MSB/LSB-first data format, 2's complement or offset binary encoding, and configurable coarse/fine gain (0–6 dB). The device operates over –40°C to +85°C with 3.3-V analog and digital supplies, no external decoupling required for internal reference.

Key Specifications

Pinout & Package

ADS6223IRGZT is housed in a 48-pin QFN package (7 mm × 7 mm) with exposed thermal pad, θ_JA = 23.17 °C/W (0 LFM), and JEDEC-compliant footprint. Pin functions are validated per TI SLAS543B Rev. January 2014.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel 12-bit ADC applications.

Compared with ADS6224IRGZT and ADS6222IRGZT, the ADS6223IRGZT offers the optimal balance of 80 MSPS throughput, 71.3 dBFS SINAD, and 350 mW/channel power - making it the preferred choice for mid-tier wireless infrastructure and test equipment requiring stable performance at moderate sampling rates.

Availability

ADS6223IRGZT is available at Aetrix Electronics and suitable for base-station IF receivers, medical ultrasound beamformers, and high-speed test equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADS6223IRGZT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of leadership in high-performance data converters and signal chain solutions.

The ADS622X family was designed specifically for demanding communications infrastructure applications - delivering dual-channel synchronization, LVDS interface density, and flexible gain control to simplify wideband receiver design.

FAQ

What is the maximum sampling rate supported by the ADS6223IRGZT?

The ADS6223IRGZT supports a maximum sampling rate of 80 MSPS, as specified in TI's SLAS543B datasheet. This rate is fully characterized across the industrial temperature range (–40°C to +85°C) with AVDD = LVDD = 3.3 V and internal reference enabled. At this rate, the device maintains 71.3 dBFS SINAD and 82 dBc SFDR at 170 MHz input with 3.5 dB coarse gain. The ADS6223IRGZT is part of the pin-compatible ADS622X family, where ADS6225IRGZT (125 MSPS) and ADS6224IRGZT (105 MSPS) offer higher rates.

Does the ADS6223IRGZT require external reference decoupling capacitors?

No, the ADS6223IRGZT does not require external decoupling capacitors for its internal reference - a key design simplification confirmed in the "Features" section of the SLAS543B datasheet. The internal reference (1.0 V bottom / 2.0 V top) is stabilized via on-chip regulation and the dedicated CAP pin, which connects only to a single 10-nF capacitor to AGND. This eliminates discrete reference bypass components, reduces BOM count, and improves layout robustness in space-constrained RF modules.

How many LVDS data lanes does the ADS6223IRGZT use in 2-wire interface mode?

In 2-wire LVDS interface mode, the ADS6223IRGZT uses four differential LVDS data lanes: DA0_P/DA0_M and DA1_P/DA1_M for Channel A, and DB0_P/DB0_M and DB1_P/DB1_M for Channel B. Each channel's 12-bit parallel output is serialized into two 6-bit streams per lane, operating in DDR mode. This configuration halves the serial data rate versus 1-wire mode - for example, at 80 MSPS, the bit clock remains below 1 Gbps, easing FPGA capture timing closure without requiring ultra-high-speed I/O banks.

What is the aperture jitter specification for the ADS6223IRGZT?

The ADS6223IRGZT has an aperture jitter specification of 250 fs rms, as measured across the full industrial temperature range (–40°C to +85°C) per SLAS543B. This low jitter directly limits SNR degradation at high input frequencies - for instance, contributing to the 68.7 dBFS SINAD observed at 230 MHz input with 3.5 dB coarse gain. The value is consistent across all ADS622X variants and is independent of sampling rate within the 5–80 MSPS range, ensuring predictable performance in wideband IF sampling applications.

Can the ADS6223IRGZT operate with an external reference?

Yes, the ADS6223IRGZT supports external reference operation via the SEN pin configuration and REFP/REFM pins. When SEN is biased to 0 V or (3/8)LVDD, the device disables its internal 1.0 V/2.0 V reference and accepts an external differential reference spanning 1.45–1.55 V common-mode with ±0.1 V tolerance. This mode is used when system-level calibration or improved DC accuracy is required beyond the ±2 mV internal reference error. The ADS6223IRGZT maintains full AC performance (SINAD, SFDR) under external reference conditions as verified in the datasheet's Electrical Characteristics tables.