Texas Instruments ADS6225IRGZ25

Overview

ADS6225IRGZ25 from Texas Instruments is a dual-channel, 12-bit, 125 MSPS analog-to-digital converter with serial LVDS interface, simultaneous sample-and-hold architecture, 3.5 dB coarse gain, and programmable fine gain up to 6 dB. It operates from 3.3-V analog and digital supplies, features internal reference with external reference support, and targets high-density IF sampling in base-station receivers.

For engineers reviewing the ADS6225IRGZ25 datasheet, ADS6225IRGZ25 pinout, ADS6225IRGZ25 application, or ADS6225IRGZ25 equivalent, key selection criteria include its 125 MSPS maximum sample rate, 70.7 dBFS SINAD at 10 MHz input (0 dB gain), 79 dBc SFDR at 170 MHz (3.5 dB gain), 48-pin QFN package (7 mm × 7 mm), and dual-wire LVDS serialization supporting <1 Gbps per channel.

Technical Context

The ADS6225IRGZ25 integrates two independent 12-bit ADC cores sharing a common PLL-based clock multiplier that derives the LVDS bit clock from the input sampling clock. Its dual-wire LVDS interface serializes each channel's 12-bit data over two differential pairs, halving the data rate versus 1-wire mode and easing receiver design.

It supports flexible configuration via parallel pins (CFG1–CFG4, SEN, PDNA/PDNB) or SPI-compatible serial interface, enabling runtime control of output format (MSB/LSB first, 2's complement/offset binary), serialization ratio (12×/14×), clock capture edge, and coarse/fine gain. Internal termination, programmable LVDS current, and current doubling enhance signal integrity.

Key Specifications

Pinout & Package

ADS6225IRGZ25 is housed in a 48-pin QFN package (7 mm × 7 mm) with exposed thermal pad, rated for –40°C to +85°C operation. Pin functions are validated per TI SLAS543B Rev. January 2014.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, high-speed ADC applications.

Compared with ADS6224IRGZT and ADS62P45IRGZT, the ADS6225IRGZ25 delivers optimal balance of 125 MSPS speed, 12-bit fidelity, and 500 mW power in a production-proven 48-QFN footprint-making it ideal for volume base-station and test-equipment designs where cost, size, and thermal envelope are constrained.

Availability

ADS6225IRGZ25 is available at Aetrix Electronics and suitable for base-station IF receivers, medical ultrasound imaging, and high-speed automated test equipment requiring stable component supply across industrial temperature range (–40°C to +85°C).

Supply support for ADS6225IRGZ25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, communications, and medical markets.

The ADS6225IRGZ25 belongs to TI's ADS622X dual-channel ADC family, designed specifically for high-density, low-latency IF sampling in wireless infrastructure and test instrumentation where serial LVDS interface and flexible gain control are essential.

FAQ

What is the maximum sampling rate supported by the ADS6225IRGZ25?

The ADS6225IRGZ25 supports a maximum sampling rate of 125 MSPS, as specified in the SLAS543B datasheet under recommended operating conditions. This rate is validated across the full industrial temperature range (–40°C to +85°C) with AVDD = LVDD = 3.3 V and proper clock conditioning. At this rate, the device achieves 70.7 dBFS SINAD and 79 dBc SFDR at 170 MHz input with 3.5 dB coarse gain enabled.

Does the ADS6225IRGZ25 require external decoupling capacitors for its reference circuitry?

No, the ADS6225IRGZ25 does not require external decoupling capacitors for its internal reference, as explicitly stated in the datasheet: "No External Decoupling Required for References." The internal reference (1.0 V bottom / 2.0 V top) is fully integrated and stabilized on-die. External decoupling remains necessary for AVDD and LVDD supplies per standard high-speed ADC layout practices.

How many LVDS data pairs does the ADS6225IRGZ25 use in dual-wire mode?

In dual-wire LVDS mode, the ADS6225IRGZ25 uses four differential LVDS data pairs: DA0_P/DA0_M and DA1_P/DA1_M for channel A, and DB0_P/DB0_M and DB1_P/DB1_M for channel B. This configuration serializes each 12-bit sample across two wires per channel, halving the data rate compared to 1-wire mode and enabling reliable capture below 1 Gbps per channel.

Can the ADS6225IRGZ25 operate with an external reference, and what voltage range is supported?

Yes, the ADS6225IRGZ25 supports external reference mode via the REFP/REFM pins. When configured for external reference, the common-mode voltage VCM must be set to 1.45–1.55 V, as specified in the recommended operating conditions table. The device maintains full 12-bit linearity and dynamic performance (e.g., 70.7 dBFS SINAD) under external reference operation, verified across temperature and supply variations.

What is the ADC latency of the ADS6225IRGZ25, and how is it defined?

The ADS6225IRGZ25 has a fixed ADC latency of 12 clock cycles, as shown in Figure 1 of the SLAS543B datasheet. This latency represents the delay from the input clock rising edge to valid data appearing at the LVDS outputs, excluding serializer latency which depends on interface mode. Total latency includes both ADC core and serializer stages; for dual-wire DDR mode, the combined latency remains deterministic and reproducible across operating conditions.