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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADS6225IRGZT

Name: ADS6225IRGZT
Brand: Texas Instruments
SKU: ADS6225IRGZT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADS6225IRGZT

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 48-VFQFN Exposed Pad

Datasheet:: ADS6225IRGZT.pdf

Description:: IC ADC 12BIT PIPELINED 48VQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

ADS6225IRGZT from Texas Instruments is a dual-channel, 12-bit, 125 MSPS analog-to-digital converter with serial LVDS interface, simultaneous sample-and-hold architecture, 3.5 dB coarse gain, and internal reference. It delivers 70.7 dBFS SINAD and 90 dBc SFDR at 10 MHz input (0 dB gain), operating from 3.3-V analog/digital supplies in industrial temperature range (–40°C to 85°C). It is used in base-station IF receivers requiring high-density signal acquisition with low jitter and serialized data output.

For engineers reviewing the ADS6225IRGZT datasheet, ADS6225IRGZT pinout, ADS6225IRGZT application, or ADS6225IRGZT equivalent, this page provides verified specifications, QFN-48 package mapping, LVDS timing constraints, dual-channel latency (12 clock cycles), and validated alternative ADCs for IF sampling systems where SFDR >85 dBc and aperture jitter <250 fs rms are critical selection criteria.

Technical Context

The ADS6225IRGZT implements two independent 12-bit SAR-based ADC cores with simultaneous sampling, each feeding a digital encoder and serializer. Its PLL multiplies the input clock to generate a DDR bit clock for 14× serialized LVDS output, supporting both 1-wire and 2-wire interface modes. The device supports programmable fine gain (±6 dB in 1-dB steps) and coarse gain (0 dB or 3.5 dB) to optimize SFDR/SNR trade-offs.

It features dual LVDS output lanes per channel (DA0_P/M, DA1_P/M, DB0_P/M, DB1_P/M), frame/bit clocks (FCLKP/M, DCLKP/M), and flexible configuration via parallel pins (CFG1–CFG4, SEN, PDNA/PDNB) or SPI-like serial interface (SEN/SCLK/SDATA). Internal termination options and programmable LVDS current improve signal integrity without external resistors.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12-bit - guarantees no missing codes across –40°C to 85°C; enables precise amplitude quantization in IF band applications.
Max Sampling Rate	125 MSPS - supports Nyquist sampling of signals up to 62.5 MHz; sufficient for wideband IF digitization in LTE/WCDMA base stations.
SINAD @ 10 MHz	70.7 dBFS (0 dB gain) - defines effective dynamic range for small-signal fidelity in medical imaging front-ends.
SFDR @ 10 MHz	90 dBc (0 dB gain) - determines spurious-free bandwidth for receiver blocking immunity in diversity receiver architectures.
Aperture Jitter	250 fs rms - limits SNR degradation at high input frequencies; critical for >100 MHz IF sampling accuracy.
Power per Channel	500 mW - total power at 125 MSPS; enables thermal management in compact 7 mm × 7 mm QFN packages.
Analog Input Bandwidth	500 MHz - supports direct sampling of first IF stages without external anti-alias filtering beyond 250 MHz.

Pinout & Package

ADS6225IRGZT is housed in a 48-pin QFN package (7 mm × 7 mm) with exposed thermal pad, θ_JA = 23.17 °C/W (0 LFM), and RoHS-compliant lead finish. Pin functions are defined per TI SLAS543B Rev. January 2014.

Pin/Terminal	Circuit Role	Design Meaning
INA_P / INA_M	Differential analog input A	Accepts 2 Vpp differential signal; common-mode voltage fixed at 1.5 V in internal reference mode.
INB_P / INB_M	Differential analog input B	Independent second channel; matched gain/phase tracking enables I/Q demodulation without calibration.
CLKP / CLKM	Differential sampling clock input	Accepts LVPECL/LVDS/LVCMOS; minimum amplitude 400 mVpp; supports duty cycle 35%–65%.
FCLKP / FCLKM	LVDS frame clock output	Indicates start of new data frame; synchronized to ADC sampling edge; aids deserializer alignment.
DCLKP / DCLKM	LVDS bit clock output	DDR clock derived from PLL; frequency = sampling rate × serialization factor (14×); used for data capture.
DA0_P / DA0_M DA1_P / DA1_M DB0_P / DB0_M DB1_P / DB1_M	LVDS serialized data outputs	2-wire interface: DA0/DA1 carry Channel A data; DB0/DB1 carry Channel B data; MSB/LSB and format configurable.
PDNA / PDNB	Channel A/B power-down control	Logic-high disables respective ADC core; reduces power by ~237 mA (A) or ~237 mA (B) in global standby.
SEN / SCLK / SDATA	Serial configuration interface	3-wire SPI-compatible bus for register access; supports full device reconfiguration without reset.
CFG1–CFG4	Parallel configuration inputs	Voltage-selectable modes for interface type (1-/2-wire), serialization (12×/14×), data order (MSB/LSB), and format (2's complement/offset binary).
REFP / REFM	Internal reference top/bottom	Provide 2.0 V and 1.0 V rails; ΔVREF error ±2 mV ensures <0.1% full-scale gain error over temperature.
VCM	Common-mode output reference	1.5 V output; drives external circuitry requiring stable bias; 4 mA drive capability supports RC filtering.
AVDD / LVDD	Analog / LVDS supply	Separate 3.3-V domains isolate noise-sensitive analog core from high-speed digital output buffers.

Key Features

Feature	Design Value
Simultaneous Sample-and-Hold	Enables true time-aligned dual-channel acquisition for I/Q or diversity reception without inter-channel skew compensation.
Programmable Coarse + Fine Gain	3.5 dB coarse gain improves SFDR by ≥10 dB at 170 MHz while preserving >67 dBFS SINAD; fine gain adjusts in 1-dB steps for system-level dynamic range tuning.
2-Wire LVDS Interface	Halves serial data rate vs. 1-wire mode (e.g., 875 Mbps at 125 MSPS), easing FPGA receiver design and reducing PCB routing complexity.
Internal PLL with Programmable Bit Clock	Eliminates need for external clock multiplier; bit clock phase aligns to sampling edge, minimizing timing uncertainty in high-speed capture.
No External Decoupling for Reference	Internal reference operates without external capacitors, reducing BOM count and board area in space-constrained RF modules.
Configurable Power-Down Modes	Per-channel (PDNA/PDNB) and global (SCLK/SDATA HIGH) power-down reduce idle power to 77 mW, extending runtime in portable test equipment.

Applications

Base-Station IF Receivers	Diversity Receivers
Use Scenario: Digitizing 70–140 MHz IF signals from RF front-end in macrocell LTE base stations with dual-polarized antennas. IC Role / Device Role / Timing Role: Dual-channel ADC captures I/Q components simultaneously; 125 MSPS sampling supports 60 MHz instantaneous bandwidth; LVDS serialization interfaces directly to Xilinx Kintex-7 FPGA. Use Value: 90 dBc SFDR prevents adjacent-channel interference; 250 fs aperture jitter maintains EVM <2.5% at 20 MHz channel spacing.	Use Scenario: Parallel digitization of signals from spatially separated antennas in MIMO wireless infrastructure. IC Role / Device Role / Timing Role: Two matched ADC channels acquire uncorrelated RF paths; channel-to-channel delay variation <±80 ps ensures coherent combining without real-time skew correction. Use Value: Identical gain/offset specs across channels (<±0.3% gain error) eliminate need for per-path calibration firmware.
Medical Ultrasound Imaging	Automated Test Equipment
Use Scenario: Beamforming front-end in portable ultrasound systems digitizing 5–15 MHz echo returns from phased-array transducers. IC Role / Device Role / Timing Role: High-SFDR conversion preserves weak tissue reflections amid strong clutter; 70.7 dBFS SINAD ensures >12-bit ENOB for grayscale depth resolution. Use Value: 500 MHz analog input bandwidth allows direct sampling without intermediate downconversion, simplifying analog signal chain.	Use Scenario: High-speed waveform capture in benchtop oscilloscopes and signal analyzers requiring >100 MSPS real-time sampling. IC Role / Device Role / Timing Role: ADC core feeds FPGA-based FFT engine; LVDS outputs clocked at 875 Mbps sustain 125 MSPS throughput with deterministic latency (12 cycles). Use Value: Wake-up time <100 μs after clock restart enables rapid measurement sequencing in automated production test fixtures.

Base-Station IF Receivers

Diversity Receivers

Use Scenario: Digitizing 70–140 MHz IF signals from RF front-end in macrocell LTE base stations with dual-polarized antennas.

IC Role / Device Role / Timing Role: Dual-channel ADC captures I/Q components simultaneously; 125 MSPS sampling supports 60 MHz instantaneous bandwidth; LVDS serialization interfaces directly to Xilinx Kintex-7 FPGA.

Use Value: 90 dBc SFDR prevents adjacent-channel interference; 250 fs aperture jitter maintains EVM <2.5% at 20 MHz channel spacing.

Use Scenario: Parallel digitization of signals from spatially separated antennas in MIMO wireless infrastructure.

IC Role / Device Role / Timing Role: Two matched ADC channels acquire uncorrelated RF paths; channel-to-channel delay variation <±80 ps ensures coherent combining without real-time skew correction.

Use Value: Identical gain/offset specs across channels (<±0.3% gain error) eliminate need for per-path calibration firmware.

Medical Ultrasound Imaging

Automated Test Equipment

Use Scenario: Beamforming front-end in portable ultrasound systems digitizing 5–15 MHz echo returns from phased-array transducers.

IC Role / Device Role / Timing Role: High-SFDR conversion preserves weak tissue reflections amid strong clutter; 70.7 dBFS SINAD ensures >12-bit ENOB for grayscale depth resolution.

Use Value: 500 MHz analog input bandwidth allows direct sampling without intermediate downconversion, simplifying analog signal chain.

Use Scenario: High-speed waveform capture in benchtop oscilloscopes and signal analyzers requiring >100 MSPS real-time sampling.

IC Role / Device Role / Timing Role: ADC core feeds FPGA-based FFT engine; LVDS outputs clocked at 875 Mbps sustain 125 MSPS throughput with deterministic latency (12 cycles).

Use Value: Wake-up time <100 μs after clock restart enables rapid measurement sequencing in automated production test fixtures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit, high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS6224IRGZT	105 MSPS max rate; 405 mW power; 91 dBc SFDR @10 MHz (0 dB gain)	Lower sampling rate suits cost-sensitive 4G small cells with <50 MHz IF bandwidth	Select when system clock budget limits to ≤105 MSPS and 125 MSPS headroom is unnecessary.
ADS5272IPFP	8-channel, 12-bit, 65 MSPS; 3.3-V supply; 72 dBFS SINAD; QFP-80 package	Higher channel count for multi-beam radar or dense sensor arrays; larger footprint and higher layout complexity	Choose for applications needing ≥8 synchronized channels where board space permits larger package.

Compared with ADS6224IRGZT and ADS5272IPFP, the ADS6225IRGZT uniquely balances 125 MSPS speed, dual-channel precision, and 7 mm × 7 mm QFN integration-making it optimal for space-constrained, wideband IF digitization where single-device channel count and jitter performance are decisive.

Availability

ADS6225IRGZT is available at Aetrix Electronics and suitable for base-station IF receivers, medical ultrasound front-ends, and automated test equipment requiring stable component supply, long-term obsolescence planning, and traceable sourcing for industrial-grade deployments.

Supply support for ADS6225IRGZT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, communications, and medical markets.

The ADS622X family-including ADS6225IRGZT-is designed for high-density, high-fidelity IF sampling in wireless infrastructure and instrumentation, emphasizing low jitter, serialized LVDS output, and flexible gain programming to simplify RF receiver design.

FAQ

What is the maximum sampling rate supported by ADS6225IRGZT?

The ADS6225IRGZT supports a maximum sampling rate of 125 MSPS, as specified in the absolute maximum ratings and electrical characteristics tables of the TI SLAS543B datasheet. This rate is achievable across the full industrial temperature range (–40°C to 85°C) with AVDD = LVDD = 3.3 V and proper clock conditioning. At this rate, the device maintains 70.7 dBFS SINAD and 90 dBc SFDR at 10 MHz input frequency with 0 dB coarse gain. Exceeding 125 MSPS is not guaranteed and may violate timing margins.

Does ADS6225IRGZT require external decoupling capacitors for its internal reference?

No, the ADS6225IRGZT does not require external decoupling capacitors for its internal reference. As stated in the FEATURES section of the SLAS543B datasheet, "No External Decoupling Required for References." The internal reference (VREFT = 2.0 V, VREFB = 1.0 V) is fully self-contained and stable across temperature and supply variations, eliminating the need for external bypass capacitors and reducing BOM count and PCB area in compact designs.

What LVDS interface modes does ADS6225IRGZT support?

The ADS6225IRGZT supports both 1-wire and 2-wire LVDS interface modes, selectable via CFG1 pin configuration. In 2-wire mode, each ADC channel uses two differential pairs (e.g., DA0_P/M and DA1_P/M for Channel A), halving the serial data rate versus 1-wire-e.g., 875 Mbps at 125 MSPS with 14× serialization. Frame and bit clocks (FCLKP/M, DCLKP/M) are always transmitted as LVDS outputs regardless of mode, ensuring deterministic timing for FPGA capture logic.

How is channel synchronization handled in ADS6225IRGZT?

The ADS6225IRGZT implements true simultaneous sample-and-hold for both channels, with channel-to-channel aperture delay variation specified at ±80 ps over temperature. This tight matching eliminates inter-channel skew in I/Q or diversity applications. No external synchronization signals are needed-the internal SHA circuits are driven by the same clock edge, and latency is identical (12 clock cycles) for both channels, enabling coherent signal processing without post-acquisition alignment.

Can ADS6225IRGZT operate with an external reference?

Yes, the ADS6225IRGZT supports external reference operation. When the SEN pin is biased to 0 V or (3/8)LVDD, the device uses external reference inputs applied to REFP and REFM pins. In this mode, full-scale input range becomes 2 Vpp (0 V SEN) or 1.34 Vpp (3/8 LVDD SEN), and VCM remains at 1.5 V. External reference mode is confirmed in Table 6 (SEN Control Pin) and the DESCRIPTION section of SLAS543B, allowing system designers to substitute precision external references for improved gain stability.

ADS6225IRGZT Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 48-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Number of Bits:: 12

Sampling Rate (Per Second):: 125M

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: LVDS - Serial

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 2

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 3V ~ 3.6V

Voltage - Supply, Digital:: 3V ~ 3.6V

Features:: Simultaneous Sampling

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 48-VQFN (7x7)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADS6225IRGZT FAQ

1.How can I place an order for ADS6225IRGZT through Aetrix?

Please submit a Request for Quotation (RFQ) for ADS6225IRGZT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADS6225IRGZT reliable?

The price and inventory of ADS6225IRGZT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6225IRGZT is usually 5 days.

3.What payment methods are accepted for ADS6225IRGZT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6225IRGZT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADS6225IRGZT?

ADS6225IRGZT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADS6225IRGZT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADS6225IRGZT?

For technical support, including ADS6225IRGZT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6225IRGZT requirements.

6.How does Aetrix verify that ADS6225IRGZT is sourced from the original manufacturer or authorized distributors?

All ADS6225IRGZT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6225IRGZT meets industry standards.

7.What is the process for return or replacement of ADS6225IRGZT?

All ADS6225IRGZT units undergo pre-shipment inspection (PSI). If there is an issue with ADS6225IRGZT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADS6225IRGZT part is unused and in its original packaging.

Return procedure for ADS6225IRGZT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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