Texas Instruments ADS62C17EVM

Overview

ADS62C17EVM from Texas Instruments is an evaluation module designed to characterize the ADS62C17 dual-channel, 11-bit, 160-MSPS analog-to-digital converter under real-world signal, clock, reference, and power supply conditions. It supports transformer-coupled or THS4509-amplified analog inputs, multiple clocking paths (direct SMA, crystal-filtered LVCMOS, or differential LVPECL), and configurable 1.8-V/3.3-V digital supply rails. The EVM enables FFT-based performance validation for IF sampling applications up to 160 MSPS.

For engineers reviewing the ADS62C17EVM datasheet, ADS62C17EVM pinout, ADS62C17EVM application, or ADS62C17EVM equivalent, this module provides hardware-level control over ADC operational mode (parallel vs. SPI), input coupling path, clock source selection, power topology (LDO-only or cascaded switching+LDO), and analog front-end biasing - all via validated jumper configurations documented in SLAU237A.

Technical Context

The ADS62C17EVM implements a dual-path analog input architecture: one path uses Mini-Circuits ADT4-1WT transformers for direct AC-coupled single-ended-to-differential conversion (default), while the second path routes signals through a THS4509 fully differential amplifier with selectable AC/DC coupling and external band-pass filtering. Power delivery supports three distinct topologies - LDO-only (5.1–5.5 V input), cascaded TPS5420D + TPS79501 (6–36 V input), or isolated AVDD/DVDD supplies for current-consumption measurement.

Clock routing includes three mutually exclusive options: (1) direct single-ended clock injection at J19, stepped up by transformer and AC-coupled to the ADC; (2) crystal-filtered 245.76 MHz LVCMOS output from CDCE72010 Y0 (configured for ×4 VCXO division); or (3) differential LVPECL output on Y1P/Y1N - all controlled by surface-mount jumpers SJP4, SJP6, SJP7, and JP21 per Table 7 of SLAU237A.

Key Specifications

Availability

ADS62C17EVM is available at Aetrix Electronics and suitable for high-speed data acquisition, IF sampling receiver design, and wideband ADC characterization requiring stable component supply, traceable sourcing, and long-term lifecycle support.

Supply support for ADS62C17EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data converter technologies.

The ADS62C17EVM belongs to TI's precision high-speed ADC evaluation platform family, engineered to accelerate validation of RF-sampling and IF-digitizing systems in communications infrastructure, test equipment, and radar applications.

FAQ

What is the primary function of the ADS62C17EVM?

The ADS62C17EVM is a dedicated evaluation module for the ADS62C17 dual-channel, 11-bit, 160-MSPS analog-to-digital converter. It provides full hardware configurability - including analog input coupling, clock source selection, power topology, and interface mode - to validate ADC performance across signal integrity, jitter sensitivity, SNR, and SFDR metrics under realistic operating conditions. The ADS62C17EVM does not operate as a standalone product but serves exclusively as a test platform for the ADS62C17 IC.

Which ADC models does the ADS62C17EVM support besides ADS62C17?

The ADS62C17EVM supports the entire ADS62PXX family, including ADS62P42/43/44/45/48/49, ADS62P22/23/24/25/28/29, and ADS62C15/17. Its jumper-based configuration accommodates differing digital supply requirements: ADS62C17 and ADS62P48/49/28/29 require 1.8-V DVDD (set via JP18), while others use 3.3-V DVDD. All supported devices share identical pinout, interface timing, and PCB footprint on the EVM.

How is clocking configured on the ADS62C17EVM?

Clocking on the ADS62C17EVM is configured using surface-mount jumpers per Table 7 of SLAU237A. Default operation uses direct single-ended clock injection at SMA connector J19 (SJP4=1–2, SJP7=1–2). Alternative modes enable crystal-filtered 245.76 MHz LVCMOS (SJP4=2–3, SJP7=3–4) or differential LVPECL (SJP4=2–3, SJP7=5–6, SJP6=2–3) from the onboard CDCE72010 clock buffer. The VCXO and crystal filter are unpopulated by default and must be added per application needs.

Can the ADS62C17EVM be used with FPGA capture platforms?

Yes, the ADS62C17EVM is explicitly designed for interoperability with TI's TSW1200 and TSW1100 FPGA-based capture boards. J8 provides a 40-pin header with parallel LVDS/CMOS data outputs, frame/line clocks, and control signals compatible with TSW1200's ADC interface. The ADS62C17EVM User's Guide (SLAU237A) includes step-by-step setup instructions, GUI configuration guidance, and FFT test procedures specifically for TSW1200 integration.

What power supply options does the ADS62C17EVM offer?

The ADS62C17EVM offers three jumper-selectable power topologies: (1) LDO-only (5.1–5.5 V at J10, default), (2) cascaded TPS5420D switching regulator + TPS79501 LDO (6–36 V at J10), and (3) isolated AVDD/DVDD supplies for current-consumption measurement (requires external 3.3-V and 1.8-V sources applied to JP15/JP18 center pins). Each option is validated in SLAU237A Tables 2–3 and supports precise noise and efficiency trade-off analysis.