Texas Instruments ADS62P23EVM

Overview

ADS62P23EVM from Texas Instruments is an evaluation module designed to characterize the ADS62P23 dual-channel, 12-bit, 65-MSPS analog-to-digital converter under controlled signal, clock, reference, and power supply conditions. It supports transformer-coupled or THS4509-amplified analog inputs, multiple clocking options (direct SMA, VCXO + CDCE72010 with crystal filter), and configurable 3.3V/1.8V digital supply rails. The EVM enables FFT-based performance validation for IF sampling applications up to 100 MHz.

For engineers reviewing the ADS62P23EVM datasheet, ADS62P23EVM pinout, ADS62P23EVM application, or ADS62P23EVM equivalent, this page provides verified hardware configuration details, jumper-controlled operational modes (parallel vs. SPI register control), clock distribution paths (LVPECL/CMOS), analog input routing options, and power architecture (TPS5420D + TPS79501 cascaded or LDO-only), all confirmed against SLAU237A User's Guide and TI schematic documentation.

Technical Context

The ADS62P23EVM implements a modular signal chain: analog inputs route via Mini-Circuits ADT4-1WT transformers or THS4509 differential amplifiers; clocking supports direct single-ended 1.5V_PP sinusoid input at J19 or onboard 983.04 MHz VCXO divided by 4 in the CDCE72010 to generate 245.76 MHz filtered LVCMOS output; power delivery includes dual-path regulation-cascaded TPS5420D (6–36 V input) + TPS79501 (5 V AVDD) + TPS79633 (3.3 V DVDD), or direct LDO-based 5.1–5.5 V input.

Jumper-configurable operation includes parallel-mode ADC control (JP11 = 1–2), SPI register access (JP22 unshunted), transformer-coupled vs. amplified input selection (SJP1/SJP2/SJP3/SJP5), and clock source routing (SJP4/SJP6/SJP7). All configurations are validated in SLAU237A Section 2.2 and schematics Sheets 1–6.

Key Specifications

Availability

ADS62P23EVM is available at Aetrix Electronics and suitable for high-speed data acquisition system validation, RF receiver IF sampling characterization, and ADC driver interface testing requiring stable component supply and documented evaluation infrastructure.

Supply support for ADS62P23EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data conversion technologies, with over 90 years of innovation in precision signal chain solutions.

The ADS62P23EVM belongs to TI's high-speed ADC evaluation platform family, engineered specifically to accelerate time-to-test for dual-channel, medium-bandwidth ADCs used in communications infrastructure, test equipment, and medical imaging front-ends.

FAQ

What is the primary function of the ADS62P23EVM?

The ADS62P23EVM is a hardware evaluation platform for the ADS62P23 dual-channel 12-bit 65-MSPS analog-to-digital converter. It provides configurable analog input paths (transformer-coupled or THS4509-amplified), multiple clocking architectures (direct SMA, VCXO + CDCE72010), and dual-mode power delivery (switching + LDO or LDO-only) to enable comprehensive performance validation-including SNR, SFDR, and ENOB-under real-world signal, timing, and supply conditions. The ADS62P23EVM is not a production component but a test vehicle for system-level ADC integration.

Which ADC models does the ADS62P23EVM support beyond the ADS62P23?

The ADS62P23EVM supports the full ADS62PXX family as stated in SLAU237A Section 1: ADS62P42/43/44/45/48/49, ADS62P22/23/24/25/28/29, and ADS62C15/17. Each variant shares identical pinout, power rail requirements (3.3 V or 1.8 V DVDD), and interface protocols, allowing the same ADS62P23EVM board to evaluate all listed devices via jumper reconfiguration-no PCB redesign required. The ADS62P23EVM's bill of materials and schematic (Sheet 1–5) are explicitly designed for this cross-compatible footprint.

How do I configure the ADS62P23EVM for transformer-coupled analog input?

To configure the ADS62P23EVM for transformer-coupled analog input, set SJP1 = 1–2 (AMPOUT+ bypassed), SJP2 = 1–2 (AMPOUT– bypassed), SJP3 = no shunt (INPUT +ve select disabled), SJP5 = 1–2 (INPUT –ve select from J3), and JP3 = 2–3 (THS4509 powered down). This routes the single-ended signal from J3 (Channel B) or J6 (Channel A) through the ADT4-1WT transformer pair directly to the ADS62P23 ADC inputs. This is the factory-default configuration documented in Table 5 (Option 1) of SLAU237A.

Can the ADS62P23EVM generate its own clock signal without external equipment?

Yes-the ADS62P23EVM can generate its own clock using the onboard VCXO and CDCE72010 clock buffer. With J18 = 1–2 (VCXO enabled), SJP4 = 2–3 (J19 supplies 20 MHz reference), SJP7 = 3–4 (Y0 output routed to ADC), and J14 open (CDCE72010 active), the CDCE72010 divides the 983.04 MHz VCXO by 4 to produce a 245.76 MHz LVCMOS clock filtered through the on-board crystal. This eliminates dependency on external clock sources during lab validation, as confirmed in SLAU237A Section 2.2.4.2 and Figure 11.

What power supply options are available for the ADS62P23EVM, and how do they differ?

The ADS62P23EVM offers three power supply options: Option 1 (JP16 = 1–2, JP17 = 1–2, JP19 = 2–3) uses TPS5420D (6–36 V input) + TPS79501 (5 V AVDD) + TPS79633 (3.3 V DVDD) for high-efficiency, low-noise operation; Option 2 (JP16 = 1–2, JP17 = no shunt, JP19 = 1–2) uses only TPS79633/TPS79601 LDOs (5.1–5.5 V input) for simplicity and low ripple; Option 3 (JP15/JP18 unshunted) isolates AVDD/DVDD for precise current consumption measurement. All options are detailed in SLAU237A Tables 2–3.