Texas Instruments ADS62P23IRGCR

Overview

ADS62P23IRGCR from Texas Instruments is a dual-channel, 12-bit analog-to-digital converter with 80 MSPS maximum sampling rate, DDR LVDS or parallel CMOS outputs, and integrated digital processing block (offset/fine gain correction, decimation, 24-tap programmable filters). It features 93 dBc SFDR at 10 MHz input (0 dB gain), 71.5 dBFS SINAD, 95 dB crosstalk, and operates from –40°C to 85°C in wireless infrastructure and SDR receivers.

For engineers reviewing the ADS62P23IRGCR datasheet, ADS62P23IRGCR pinout, ADS62P23IRGCR application, or ADS62P23IRGCR equivalent, this page delivers verified specifications, package mapping, functional alternatives, and design-critical timing and power data - all confirmed for the exact ADS62P23IRGCR variant per TI SLAS576C (Rev. October 2011).

Technical Context

The ADS62P23IRGCR implements a dual-sampling architecture with independent sample-and-hold circuits per channel, low-jitter internal clock buffer, and configurable coarse (3.5 dB) and fine (0.05 dB steps) gain control to optimize SNR/SFDR trade-offs at reduced full-scale input ranges. Its digital processing block supports decimation by 2/4/8 and built-in or custom 24-tap FIR filtering - all programmable via serial interface or parallel control pins.

It supports multiple clock inputs (sine, LVPECL, LVDS, LVCMOS) down to 400 mV_PP, includes a clock duty cycle stabilizer, and offers flexible reference options: internal (1 V–2 V) or external (1.45–1.55 V common-mode). Output interfaces are pin-selectable between DDR LVDS (3.3 V DRVDD) and parallel CMOS (1.8–3.6 V DRVDD), with programmable drive strength and multiplexed mode support.

Key Specifications

Pinout & Package

ADS62P23IRGCR uses a 64-pin QFN package (RGC designation) with 0.5 mm pitch, 9 mm × 9 mm body, and exposed thermal pad. Pin functions are defined per TI SLAS576C Figure 1 and Table 3–6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel, 12-bit ADC applications.

Compared with ADS62P24IRGCR and ADS62P22IRGCR, the ADS62P23IRGCR delivers optimal balance of sampling speed (80 MSPS), SFDR (93 dBc), and power (594 mW) - making it ideal for mid-tier wireless infrastructure and SDR platforms where 105 MSPS is unnecessary but 65 MSPS is insufficient.

Availability

ADS62P23IRGCR is available at Aetrix Electronics and suitable for wireless communications infrastructure, software-defined radio, and power amplifier linearization requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for ADS62P23IRGCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-performance data converters and signal chain solutions.

The ADS62P2X family - including ADS62P23IRGCR - was designed specifically for demanding communications applications requiring dual-channel synchronization, flexible digital processing, and low-power, high-SFDR digitization in compact form factors.

FAQ

What is the maximum sampling rate supported by the ADS62P23IRGCR?

The ADS62P23IRGCR supports a maximum sampling rate of 80 MSPS, as specified in TI SLAS576C (Rev. October 2011). This rate is validated across the full industrial temperature range (–40°C to 85°C) with AVDD = 3.3 V and proper clock conditioning. Exceeding 80 MSPS may result in degraded SFDR or increased aperture jitter beyond datasheet limits.

Does the ADS62P23IRGCR support both LVDS and CMOS output interfaces?

Yes, the ADS62P23IRGCR supports both DDR LVDS and parallel CMOS output interfaces. Interface selection is controlled via the SEN pin voltage level per Table 5 of SLAS576C. DDR LVDS requires DRVDD = 3.0–3.6 V and external 100 Ω termination; CMOS supports DRVDD = 1.8–3.6 V with programmable drive strength.

What is the SFDR performance of the ADS62P23IRGCR at 10 MHz input frequency?

The ADS62P23IRGCR achieves 93 dBc SFDR at 10 MHz input frequency with 0 dB gain, as measured under typical conditions (AVDD = 3.3 V, FS = 80 MSPS, internal reference). This value is confirmed in Table 1 of SLAS576C and represents worst-case spurious content relative to full-scale fundamental tone.

Can the ADS62P23IRGCR operate with an external reference voltage?

Yes, the ADS62P23IRGCR supports external reference operation. When configured via SCLK pin voltage (Table 4), the device accepts an external reference with common-mode voltage of 1.45–1.55 V applied to the VCM pin. Internal reference remains available as default, eliminating need for external reference ICs in most applications.

What package type and pin count does the ADS62P23IRGCR use?

The ADS62P23IRGCR uses a 64-pin QFN package (RGC designation), measuring 9 mm × 9 mm with 0.5 mm pitch and an exposed thermal pad. This package is documented in TI's SLAS576C Package/Ordering Information section and is shared across the ADS62P2X family for footprint compatibility.