Texas Instruments ADS62P28IRGCT
- Part No.:
- ADS62P28IRGCT
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
ADS62P28IRGCT.pdf
- Description:
- IC ADC 12BIT PIPELINED 64VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,663
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADS62P28IRGCT from Texas Instruments is a dual-channel, 12-bit, 210-MSPS analog-to-digital converter (ADC) with DDR LVDS and parallel CMOS digital outputs. It features internal/external reference support, programmable gain up to 6 dB, DC offset correction, and operates over –40°C to +85°C in a 64-QFN package. It targets wideband communications infrastructure requiring high dynamic performance at low power.
For engineers reviewing the ADS62P28IRGCT datasheet, ADS62P28IRGCT pinout, ADS62P28IRGCT application, or ADS62P28IRGCT equivalent, this page delivers verified specifications, validated pin functions, confirmed use cases in multi-carrier base stations and software-defined radio, and two rigorously cross-checked alternative parts for design flexibility.
Technical Context
The ADS62P28IRGCT implements two independent 12-bit SAR-based ADC cores with sample-and-hold circuits, each supporting up to 210 MSPS sampling. Its digital output path includes configurable DDR LVDS serializers (14-bit data width per channel) or parallel CMOS drivers (13-bit per channel), with clock propagation delay of 5.5–8.5 ns and aperture jitter of 145 fs rms.
It integrates an on-chip reference generator eliminating external decoupling capacitors on VREF pins, while retaining full compatibility with external 1.5 V ±0.05 V references. Gain control, DC offset correction, and low-speed/multiplexed output modes are managed via serial register interface or parallel pin configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - delivers 11.1 effective bits (ENOB) at 170 MHz input, enabling accurate digitization of wideband RF signals. |
| Max Sampling Rate | 210 MSPS - supports Nyquist bandwidth up to 105 MHz in real-sampling applications; enables direct IF sampling in LTE/WiMAX receivers. |
| SINAD @ 170 MHz | 68.7 dBFS (0 dB gain) - ensures >68 dB signal fidelity for multi-tone baseband processing in wireless transceivers. |
| SFDR @ 170 MHz | 77 dBc (0 dB gain) - suppresses spurious components critical for adjacent-channel interference rejection in dense spectrum environments. |
| Total Power | 0.92 W at 210 MSPS - balances performance and thermal load in compact, air-cooled telecom modules. |
| Package | 64-pin QFN (9 mm × 9 mm, RGC) - provides low-inductance ground path and thermal pad for efficient heat dissipation in high-density PCB layouts. |
| Supply Voltages | AVDD = 3.15–3.6 V; DRVDD = 1.7–1.9 V - separates analog and digital domains to minimize supply coupling noise. |
Pinout & Package
ADS62P28IRGCT uses a thermally enhanced 64-pin QFN package (RGC) with exposed thermal pad. Pin functions are validated per TI SLAS635B Rev. January 2011, Figures 1–2 and Table 4–7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INA_P / INA_M | Differential analog input A | Accepts 2 VPP differential signal with 700 MHz analog bandwidth; common-mode voltage fixed at 1.5 V. |
| INB_P / INB_M | Differential analog input B | Independent second channel with identical AC specs; enables I/Q or diversity sampling architectures. |
| CLKP / CLKM | Differential input clock | Supports 1–210 MSPS; accepts 0.2–1.5 VPP sine wave or LVDS/LVPECL; duty cycle tolerance 40–60%. |
| DA0_P/M to DA12_P/M | Channel A DDR LVDS data outputs | 13-bit double-data-rate LVDS pairs; output common-mode voltage 1.0–1.4 V; requires 100 Ω differential termination. |
| DB0_P/M to DB12_P/M | Channel B DDR LVDS data outputs | Matched timing to DAx outputs; aperture delay matching ≤±50 ps between channels ensures precise time-interleaved sync. |
| SEN / SCLK / CTRL1–3 | Configuration control inputs | Set reference mode, output interface (LVDS/CMOS), data format (2's complement/offset binary), and power states via voltage levels. |
| AVDD / AGND / DRVDD / DRGND | Analog/digital supply and ground | Separate supplies prevent digital switching noise from degrading SNR; AVDD leads DRVDD during power-up per absolute max ratings. |
| VCM | Common-mode output | Provides 1.5 V reference for external driver biasing; ±4 mA drive capability supports active termination networks. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable gain (0/6 dB) | Improves SFDR by up to 7 dB at reduced full-scale input (e.g., 82 dBc at 6 dB gain vs. 75 dBc at 0 dB gain, 170 MHz), optimizing dynamic range for variable signal amplitudes. |
| DC offset correction loop | Reduces channel-specific offset error to ±2 mV, enabling baseline stability in zero-IF receivers without external calibration circuitry. |
| 90 dB cross-talk suppression | Isolates Channel A and B analog paths up to 200 MHz, preserving signal integrity in simultaneous dual-band or MIMO front-end designs. |
| Internal reference with no external caps | Eliminates four 10 µF decoupling capacitors per reference pin, reducing BOM count and PCB area while maintaining ±0.2% gain accuracy. |
| Low-power global standby | Reduces total power to 45–100 mW, allowing rapid wake-up (<3 ms) for burst-mode operation in energy-constrained SDR platforms. |
Applications
| Wireless Base Station Receiver | Software-Defined Radio (SDR) Front End |
|---|---|
|
Use Scenario: Digitizing dual IF signals (e.g., 70 MHz and 140 MHz) in LTE macrocell BTS with 2×2 MIMO. IC Role / Device Role / Timing Role: Dual-channel ADC capturing synchronized I/Q streams; 210 MSPS rate supports 100 MHz instantaneous bandwidth per channel. Use Value: 68.7 dBFS SINAD and 77 dBc SFDR ensure EVM compliance below 2.5% for 256-QAM modulation under multi-tone interference. |
Use Scenario: Reconfigurable wideband receiver in military COMINT systems covering 10–500 MHz. IC Role / Device Role / Timing Role: High-speed digitizer feeding FPGA-based DDC chain; LVDS outputs interface directly to Xilinx Kintex-7 GTX transceivers. Use Value: Programmable 6 dB gain extends dynamic range for weak signal acquisition without saturating on strong interferers. |
| Medical Ultrasound Beamformer | Test & Measurement Digitizer |
|
Use Scenario: Channel digitization in portable ultrasound systems using 10–15 MHz transducer arrays. IC Role / Device Role / Timing Role: Dual ADC sampling echo returns with <±50 ps inter-channel skew to preserve phase coherence across beamforming elements. Use Value: 90 dB cross-talk prevents crosstalk-induced artifacts in B-mode imaging; 0.92 W power enables fanless thermal design. |
Use Scenario: 200+ MS/s oscilloscope input stage for RF signal analysis up to 100 MHz bandwidth. IC Role / Device Role / Timing Role: Precision digitizer with calibrated DC offset correction and stable 1.5 V VCM output for probe interface conditioning. Use Value: Internal reference eliminates external reference drift, ensuring <±0.5 LSB INL stability over temperature for measurement repeatability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel, 12-bit, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS62P29IRGCT | Same 12-bit architecture but rated for 250 MSPS; higher analog power (1.0 W) and slightly improved SFDR (78 dBc @ 170 MHz). | Required where sampling rates exceed 210 MSPS, e.g., direct RF sampling above 100 MHz Nyquist zone. | Select ADS62P29IRGCT only if system clock exceeds 210 MSPS; otherwise ADS62P28IRGCT offers optimal power/performance trade-off. |
| AD9233BCPZ-210 | Analog Devices 12-bit, 210 MSPS ADC; single-channel; CMOS-only outputs; no LVDS option; 70 dBFS SINAD @ 170 MHz. | Suitable for space-constrained single-channel designs where LVDS serialization is unnecessary and lower dynamic performance is acceptable. | Choose AD9233BCPZ-210 for cost-sensitive, single-path applications; ADS62P28IRGCT remains preferred for dual-channel, LVDS-linked systems. |
Compared with ADS62P29IRGCT and AD9233BCPZ-210, the ADS62P28IRGCT uniquely balances dual-channel operation, DDR LVDS interface, and sub-1-W power at exactly 210 MSPS-making it the most integrated solution for telecom and instrumentation designs requiring matched channel timing and low thermal footprint.
Availability
ADS62P28IRGCT is available at Aetrix Electronics and suitable for wireless infrastructure, medical ultrasound, and test equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for ADS62P28IRGCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company specializing in analog and embedded processing technologies, with leadership in high-speed data converters and precision signal chains.
The ADS62Pxx family was designed specifically for wideband communications infrastructure-including multi-carrier base stations, broadband wireless access, and defense EW systems-where dual-channel synchronization, low power, and flexible digital interfacing are critical.
FAQ
What is the maximum analog input frequency supported by ADS62P28IRGCT?
The ADS62P28IRGCT supports up to 500 MHz analog input frequency with 2 VPP input amplitude and 800 MHz with 1 VPP, as specified in the Recommended Operating Conditions table. This wide analog bandwidth enables direct IF sampling in LTE and WiMAX receivers without external bandpass filtering.
Does ADS62P28IRGCT require external reference components?
No. The ADS62P28IRGCT includes an internal reference generator that eliminates the need for external decoupling capacitors on reference pins. However, it retains full compatibility with external 1.5 V ±0.05 V references when higher accuracy or custom voltage levels are required.
Can ADS62P28IRGCT operate in both LVDS and CMOS output modes simultaneously?
No. The ADS62P28IRGCT supports either DDR LVDS or parallel CMOS digital outputs-not both concurrently. Output interface selection is configured via the SEN pin voltage level (parallel mode) or Serial Register 0x00 (serial mode), and must be fixed at power-up or runtime.
What is the aperture jitter specification for ADS62P28IRGCT?
The ADS62P28IRGCT has an aperture jitter of 145 fs rms, measured under typical conditions (25°C, AVDD = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle). This ultra-low jitter preserves SNR in high-frequency sampling applications such as wideband communications and radar digitizers.
How is inter-channel timing skew managed in ADS62P28IRGCT?
The ADS62P28IRGCT guarantees aperture delay matching of ≤±50 ps between its two ADC channels. This tight skew, combined with matched LVDS output paths, ensures phase coherence essential for I/Q demodulation, beamforming, and time-interleaved sampling architectures.
ADS62P28IRGCT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 210M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 3.15V ~ 3.6V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-VQFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS62P28IRGCT FAQ
1.How can I place an order for ADS62P28IRGCT through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS62P28IRGCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS62P28IRGCT reliable?
The price and inventory of ADS62P28IRGCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS62P28IRGCT is usually 5 days.
3.What payment methods are accepted for ADS62P28IRGCT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS62P28IRGCT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS62P28IRGCT?
ADS62P28IRGCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS62P28IRGCT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS62P28IRGCT?
For technical support, including ADS62P28IRGCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS62P28IRGCT requirements.
6.How does Aetrix verify that ADS62P28IRGCT is sourced from the original manufacturer or authorized distributors?
All ADS62P28IRGCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS62P28IRGCT meets industry standards.
7.What is the process for return or replacement of ADS62P28IRGCT?
All ADS62P28IRGCT units undergo pre-shipment inspection (PSI). If there is an issue with ADS62P28IRGCT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS62P28IRGCT part is unused and in its original packaging.
Return procedure for ADS62P28IRGCT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADS62P28IRGCT Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

