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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADS62P49IRGCT

Name: ADS62P49IRGCT
Brand: Texas Instruments
SKU: ADS62P49IRGCT
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADS62P49IRGCT

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 64-VFQFN Exposed Pad

Datasheet:: ADS62P49IRGCT.pdf

Description:: IC ADC 14BIT PIPELINED 64VQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

ADS62P49IRGCT from Texas Instruments is a dual-channel, 14-bit, 250-MSPS analog-to-digital converter with DDR LVDS and parallel CMOS digital outputs. It features internal/external reference support, programmable gain up to 6 dB for SFDR optimization, DC offset correction, and operates over –40°C to 85°C. It targets multi-carrier wideband communications base stations requiring high dynamic performance in compact form.

For engineers reviewing the ADS62P49IRGCT datasheet, ADS62P49IRGCT pinout, ADS62P49IRGCT application, or ADS62P49IRGCT equivalent, key selection criteria include its 250-MSPS sampling rate, 73.4 dBFS SINAD at 20 MHz input (LVDS mode), 64-QFN package, dual-channel timing matching (±50 ps aperture delay skew), and support for both DDR LVDS and parallel CMOS interfaces.

Technical Context

The ADS62P49IRGCT implements two independent 14-bit pipeline ADC cores with sample-and-hold circuits, each driven by a shared differential clock input (CLKP/CLKM). Its digital output path includes configurable DDR LVDS serializers or parallel CMOS drivers, with programmable gain control and on-chip DC offset correction loop per channel.

It supports internal reference (1.5 V ±0.05 V common-mode) or external reference mode, eliminating dedicated reference pins and decoupling capacitors. Power delivery is split into AVDD (3.15–3.6 V) for analog circuitry and DRVDD (1.7–1.9 V) for digital I/O, with total power consumption of 1.25 W at 250 MSPS in LVDS mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	14-bit - delivers 11.4 ENOB at 170 MHz input, enabling high-fidelity digitization of wideband RF signals.
Max Sampling Rate	250 MSPS - supports Nyquist bandwidth up to 125 MHz; maximum recommended with CMOS interface is 210 MSPS.
SINAD @ 20 MHz	73.4 dBFS (0 dB gain, LVDS) - defines usable dynamic range for low-distortion signal capture in LTE/WiMAX receivers.
SFDR @ 170 MHz	71 dBc (0 dB gain, LVDS) - determines spurious-free operation margin in dense spectral environments.
Total Power	1.25 W at 250 MSPS - split as 1.01 W analog + 0.24 W digital (LVDS), critical for thermal management in dense PCB layouts.
Aperture Delay Skew	±50 ps between channels - ensures precise phase alignment for I/Q sampling and beamforming applications.
Input Clock Amplitude	Min 400 mV_PP differential - enables robust sampling with low-jitter clock sources without amplification.

Pinout & Package

ADS62P49IRGCT is housed in a 64-pin QFN package (RGC designation), 9 mm × 9 mm, with exposed thermal pad. Pin functions are defined per TI SLAS635B Rev. January 2011.

Pin/Terminal	Circuit Role	Design Meaning
INA_P / INA_M	Differential analog input A	Accepts 2 V_PP full-scale differential signal; 700 MHz analog bandwidth with 25 Ω source impedance.
INB_P / INB_M	Differential analog input B	Independent second channel with matched gain/offset characteristics to INA for synchronous dual-sampling.
CLKP / CLKM	Differential sampling clock input	Supports 1–250 MSPS; accepts LVDS (0.7 V_PP), LVPECL (1.6 V_PP), or ac-coupled sine wave (0.2–1.5 V_PP).
DA0_P/M to DA12_P/M DB0_P/M to DB12_P/M	DDR LVDS data outputs (A/B channels)	Double-data-rate serialized outputs; 100 Ω differential termination required; VOCM = 1.0–1.15 V.
DA0–DA13 / DB0–DB13	Parallel CMOS data outputs (A/B channels)	14-bit wide per channel; 1.8 V logic; max 210 MSPS; load capacitance ≤5 pF per pin.
VCM	Common-mode voltage reference	Outputs 1.5 V for internal reference mode; used as input for external reference configuration.
RESET	Asynchronous reset input	Active-low; resets internal registers and initiates power-on sequence; must be held high for parallel mode.
CTRL1–CTRL3	Parallel configuration control	Set global power-down, channel standby, or MUX mode via voltage levels (0 V, 3/8 AVDD, 5/8 AVDD, AVDD).

Key Features

Feature	Design Value
Programmable gain (0/6 dB)	Improves SFDR by up to 7 dB at reduced full-scale input (e.g., 82 dBc at 170 MHz with 6 dB gain), preserving SNR headroom.
DC offset correction loop	Automatically cancels channel-specific ADC offset errors (<±20 mV), reducing calibration burden in production test.
Dual-output interface	Hardware-selectable DDR LVDS or parallel CMOS - allows system-level trade-off between EMI (LVDS) and FPGA interface simplicity (CMOS).
90 dB cross-talk suppression	Ensures >90 dB isolation between channels up to 200 MHz, critical for simultaneous I/Q or diversity receiver architectures.
No external reference pins	Internal 1.5 V reference eliminates REFIO/REFGND pins and associated decoupling, reducing BOM count and layout area.

Applications

Wireless Base Station Receiver	Medical Ultrasound Beamformer
Use Scenario: Digitizing multiple RF downconverted carriers in LTE/FDD-TDD macrocells with >20 MHz instantaneous bandwidth. IC Role / Device Role: Dual-channel front-end ADC capturing synchronized I/Q paths with <±50 ps timing skew. Use Value: 73.4 dBFS SINAD and 71 dBc SFDR at 170 MHz enable high-order modulation (256-QAM) demodulation without distortion-induced BER degradation.	Use Scenario: High-frame-rate ultrasound imaging requiring real-time digitization of echo returns from 128+ transducer elements. IC Role / Device Role: Paired channel ADC acquiring time-aligned RF echoes across adjacent receive channels. Use Value: 90 dB inter-channel crosstalk and matched aperture delay ensure accurate beam synthesis and spatial resolution preservation.
Radar Signal Acquisition	Test & Measurement Digitizer
Use Scenario: Capturing wideband pulsed radar returns (L/S-band) with nanosecond timing precision for Doppler and range analysis. IC Role / Device Role: High-speed dual ADC providing phase-coherent sampling for pulse compression and STAP processing. Use Value: 250 MSPS sampling and 700 MHz analog input bandwidth support >100 MHz IF digitization without aliasing or roll-off.	Use Scenario: Modular digitizer module in automated test equipment requiring calibrated, low-noise acquisition up to 125 MHz Nyquist bandwidth. IC Role / Device Role: Precision ADC core with programmable gain and DC offset correction for self-calibrating measurement systems. Use Value: Internal reference stability (±0.05 V) and 0.02 mV/°C offset drift minimize recalibration frequency during thermal cycling.

Wireless Base Station Receiver

Medical Ultrasound Beamformer

Use Scenario: Digitizing multiple RF downconverted carriers in LTE/FDD-TDD macrocells with >20 MHz instantaneous bandwidth.

IC Role / Device Role: Dual-channel front-end ADC capturing synchronized I/Q paths with <±50 ps timing skew.

Use Value: 73.4 dBFS SINAD and 71 dBc SFDR at 170 MHz enable high-order modulation (256-QAM) demodulation without distortion-induced BER degradation.

Use Scenario: High-frame-rate ultrasound imaging requiring real-time digitization of echo returns from 128+ transducer elements.

IC Role / Device Role: Paired channel ADC acquiring time-aligned RF echoes across adjacent receive channels.

Use Value: 90 dB inter-channel crosstalk and matched aperture delay ensure accurate beam synthesis and spatial resolution preservation.

Radar Signal Acquisition

Test & Measurement Digitizer

Use Scenario: Capturing wideband pulsed radar returns (L/S-band) with nanosecond timing precision for Doppler and range analysis.

IC Role / Device Role: High-speed dual ADC providing phase-coherent sampling for pulse compression and STAP processing.

Use Value: 250 MSPS sampling and 700 MHz analog input bandwidth support >100 MHz IF digitization without aliasing or roll-off.

Use Scenario: Modular digitizer module in automated test equipment requiring calibrated, low-noise acquisition up to 125 MHz Nyquist bandwidth.

IC Role / Device Role: Precision ADC core with programmable gain and DC offset correction for self-calibrating measurement systems.

Use Value: Internal reference stability (±0.05 V) and 0.02 mV/°C offset drift minimize recalibration frequency during thermal cycling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-channel high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS62P48IRGCT	14-bit, 210-MSPS max sampling rate; lower analog power (0.92 W); identical pinout and register map.	Targeted at cost-optimized wideband receivers where 210 MSPS suffices (e.g., sub-6 GHz 5G FR1).	Select when system clock constraints or thermal budget preclude 250 MSPS operation but 14-bit resolution is mandatory.
ADS62P29IRGCT	12-bit, 250-MSPS; higher SFDR (82 dBc at 170 MHz w/6 dB gain); lower power (1.0 W); same package and interface options.	Better suited for spurious-sensitive applications like spectrum analyzers where SFDR outweighs resolution.	Choose when SFDR >75 dBc is prioritized over ENOB, and 12-bit quantization meets system SNR requirements.

Compared with ADS62P49IRGCT, ADS62P48IRGCT trades 40 MSPS for lower power and cost while retaining 14-bit fidelity, whereas ADS62P29IRGCT maintains full 250 MSPS but reduces resolution to 12 bits to achieve superior spurious performance and efficiency.

Availability

ADS62P49IRGCT is available at Aetrix Electronics and suitable for wireless infrastructure, medical ultrasound, radar signal acquisition, and automated test equipment requiring stable component supply and industrial temperature-grade performance.

Supply support for ADS62P49IRGCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS62Pxx family was designed specifically for multi-carrier, wideband communications systems demanding high dynamic range, low power, and dual-channel synchronization in space-constrained designs.

FAQ

What is the maximum sampling rate supported by the ADS62P49IRGCT?

The ADS62P49IRGCT supports a maximum sampling rate of 250 MSPS when using the DDR LVDS interface. With the parallel CMOS interface, the maximum recommended rate is 210 MSPS due to timing margins and load capacitance limitations. This specification is validated across the full industrial temperature range (–40°C to 85°C) and is documented in the SLAS635B datasheet revision January 2011.

Does the ADS62P49IRGCT require an external reference voltage?

No, the ADS62P49IRGCT does not require an external reference voltage. It includes an internal 1.5 V reference and eliminates dedicated REFIO/REFGND pins and associated decoupling capacitors. However, it can also operate with an external reference applied to the VCM pin, offering design flexibility for systems requiring tighter reference tolerance or custom common-mode levels.

How is channel-to-channel timing skew specified for the ADS62P49IRGCT?

The ADS62P49IRGCT specifies aperture delay matching between its two channels as ±50 ps over temperature and process. This tight skew enables coherent sampling for I/Q demodulation, beamforming, and time-of-flight measurements. The value is measured under standard conditions (25°C, AVDD = 3.3 V, DRVDD = 1.8 V) and is guaranteed across the full operating range per the SLAS635B datasheet.

What digital output interfaces does the ADS62P49IRGCT support?

The ADS62P49IRGCT supports two configurable digital output interfaces: DDR LVDS and parallel CMOS. Interface selection is controlled via the SEN pin in parallel mode or serial register 0x00 in serial mode. DDR LVDS provides low EMI and high noise immunity at 250 MSPS, while parallel CMOS simplifies FPGA interfacing at up to 210 MSPS with standard 1.8 V logic levels.

What is the power consumption of the ADS62P49IRGCT at full speed?

At 250 MSPS with DDR LVDS output enabled, the ADS62P49IRGCT consumes 1.25 W total power: 1.01 W analog (IAVDD = 305–350 mA at 3.3 V) and 0.24 W digital (IDRVDD = 133–175 mA at 1.8 V). Power drops to 1.0 W in global power-down mode. These values are measured under typical conditions (25°C, internal reference, 0 dB gain) and confirmed in the Electrical Characteristics tables of SLAS635B.

ADS62P49IRGCT Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Number of Bits:: 14

Sampling Rate (Per Second):: 250M

Number of Inputs:: 2

Input Type:: Differential

Data Interface:: LVDS - Parallel, Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 2

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 3.15V ~ 3.6V

Voltage - Supply, Digital:: 1.7V ~ 1.9V

Features:: Simultaneous Sampling

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 64-VQFN (9x9)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADS62P49IRGCT FAQ

1.How can I place an order for ADS62P49IRGCT through Aetrix?

Please submit a Request for Quotation (RFQ) for ADS62P49IRGCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADS62P49IRGCT reliable?

The price and inventory of ADS62P49IRGCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS62P49IRGCT is usually 5 days.

3.What payment methods are accepted for ADS62P49IRGCT?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS62P49IRGCT transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADS62P49IRGCT?

ADS62P49IRGCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADS62P49IRGCT order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADS62P49IRGCT?

For technical support, including ADS62P49IRGCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS62P49IRGCT requirements.

6.How does Aetrix verify that ADS62P49IRGCT is sourced from the original manufacturer or authorized distributors?

All ADS62P49IRGCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS62P49IRGCT meets industry standards.

7.What is the process for return or replacement of ADS62P49IRGCT?

All ADS62P49IRGCT units undergo pre-shipment inspection (PSI). If there is an issue with ADS62P49IRGCT, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADS62P49IRGCT part is unused and in its original packaging.

Return procedure for ADS62P49IRGCT:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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