Texas Instruments ADS6424IRGCT
- Part No.:
- ADS6424IRGCT
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
ADS6424IRGCT.pdf
- Description:
- IC ADC 12BIT PIPELINED 64VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADS6424IRGCT from Texas Instruments is a quad-channel, 12-bit, 105 MSPS analog-to-digital converter with serial LVDS interface, internal PLL clock multiplication, and programmable coarse/fine gain for SFDR/SNR trade-off optimization in IF sampling receivers.
For engineers reviewing the ADS6424IRGCT datasheet, ADS6424IRGCT pinout, ADS6424IRGCT application, or ADS6424IRGCT equivalent, this page delivers verified electrical specs (91 dBc SFDR at 10 MHz, 71.1 dBFS SINAD), package mapping (64-pin QFN, 9 mm × 9 mm), timing parameters (12-cycle latency, 250 fs rms aperture jitter), and validated alternatives for base-station diversity receiver and medical imaging signal chains.
Technical Context
The ADS6424IRGCT implements a 2-wire LVDS serial interface with 14× serialization and DDR bit clock, reducing data rate to <1 Gbps per channel pair while maintaining frame/bit clock synchronization. Its internal PLL multiplies the input sampling clock to generate precise bit clocks for serialization.
It supports dual configuration modes: parallel pin control (CFG1–CFG4, SEN, PDN) for hardware-defined settings like 2-wire/DDR mode and coarse gain, and serial register programming (via SEN/SCLK/SDATA) for fine-grained control of output format (MSB/LSB first, 2's complement/offset binary), deskew patterns, and power states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit with no missing codes - guarantees monotonicity and full-scale linearity across industrial temperature range. |
| Sampling Rate | 105 MSPS maximum - enables direct IF sampling of 170 MHz signals with >67 dBFS SINAD and 79 dBc SFDR at 3.5 dB coarse gain. |
| Analog Input Bandwidth | 500 MHz - supports wideband RF/IF front-end interfacing without external anti-aliasing filter degradation. |
| LVDS Interface | 2-wire DDR with programmable internal termination - halves serial data rate vs. 1-wire, eases FPGA capture and improves eye opening. |
| Power Consumption | 1.35 W total (322 mA AVDD + 88 mA LVDD) at 105 MSPS - optimized for high-density multichannel systems with thermal budget constraints. |
| Aperture Jitter | 250 fs rms - limits SNR degradation to ≤0.3 dB at 170 MHz input, critical for high-fidelity communications sampling. |
| Operating Temperature | –40°C to +85°C - qualified for industrial and base-station outdoor equipment deployment. |
Pinout & Package
ADS6424IRGCT is housed in a thermally enhanced 64-pin QFN package (RGC designation), 9 mm × 9 mm body with exposed thermal pad. Pin pitch is 0.5 mm; recommended PCB layout includes soldered thermal pad to inner ground plane for θJA = 23.17 °C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INA_P / INA_M INB_P / INB_M INC_P / INC_M IND_P / IND_M |
Differential analog inputs (4 channels) | Accepts 2 VPP differential input range; common-mode voltage fixed at 1.5 V in internal reference mode. |
| CLKP / CLKM | Differential sampling clock input | Supports sine, LVPECL, LVDS, or LVCMOS clocks down to 400 mVPP; 5–105 MSPS range with 35–65% duty cycle tolerance. |
| DCLKP / DCLKM FCLKP / FCLKM |
LVDS serialized data and frame clock outputs | DDR 2-wire interface: each channel's 12-bit data serialized over two LVDS pairs; frame clock aligns 12-bit words across all four channels. |
| DA0_P / DA0_M DB0_P / DB0_M DC0_P / DC0_M DD0_P / DD0_M (and corresponding _1 variants) |
LVDS data output pairs (per channel) | Two LVDS pairs per ADC channel carry serialized 12-bit samples; configurable MSB/LSB first and 2's complement/offset binary format. |
| SEN / SCLK / SDATA / CFG1–CFG4 / PDN / RESET | Configuration and control interface | Parallel pins (CFG1–CFG4, PDN, SEN) set boot-time defaults; serial interface (SEN/SCLK/SDATA) enables runtime register reconfiguration. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable coarse gain (0 dB / 3.5 dB) | Improves SFDR by up to 3 dB at 170 MHz input without degrading SNR beyond 0.5 dB - enables dynamic range optimization in noise-limited receivers. |
| 14× serialization with DDR LVDS | Reduces per-channel serial data rate to 735 Mbps at 105 MSPS - relaxes FPGA I/O timing closure and reduces interconnect loss sensitivity. |
| Internal reference with external reference support | Eliminates need for external reference decoupling; ±2 mV reference error allows <±0.1% gain accuracy - simplifies BOM and layout in space-constrained designs. |
| Configurable output data format | MSB/LSB first and 2's complement/offset binary selection via CFG4 or register - ensures compatibility with diverse FPGA DSP pipelines and legacy processor interfaces. |
| Global and channel-level power-down | Reduces power to 77 mW in global power-down state; wake-up time <100 μs - enables rapid duty-cycled operation in battery-assisted test equipment. |
Applications
| Base-Station IF Receivers | Diversity Receivers |
|---|---|
|
Use Scenario: Digitizing 70–170 MHz IF signals from multiple antenna paths in LTE/FDD/TDD macro base stations. IC Role / Device Role / Timing Role: Quad-channel simultaneous sampling ADC with 105 MSPS rate and 500 MHz analog bandwidth provides coherent multi-path capture for MIMO processing. Use Value: 91 dBc SFDR at 10 MHz and 79 dBc at 170 MHz enables clean adjacent-channel rejection; 250 fs aperture jitter preserves EVM under high-order QAM modulation. |
Use Scenario: High-speed digitization of dual-polarized or spatially separated RF signals in 5G NR active antenna systems. IC Role / Device Role / Timing Role: Four synchronized ADC channels deliver phase-coherent samples across independent receive paths for real-time beamforming and interference cancellation. Use Value: Channel-channel aperture delay variation <±80 ps ensures sub-degree phase alignment; LVDS serialization minimizes skew between channel data streams. |
| Medical Ultrasound Imaging | Automated Test Equipment |
|
Use Scenario: Capturing echo return signals from phased-array transducers operating at 2–15 MHz center frequencies with >100 dB dynamic range requirements. IC Role / Device Role / Timing Role: Low-noise, high-SFDR ADC enabling 12-bit effective resolution at 105 MSPS for time-of-flight and Doppler shift analysis. Use Value: 71.1 dBFS SINAD at 10 MHz and 67.4 dBFS at 170 MHz supports deep tissue penetration imaging; internal reference eliminates external reference drift-induced gain error. |
Use Scenario: High-accuracy waveform acquisition in modular PXI or LXI-based ATE platforms requiring multi-channel synchronous sampling. IC Role / Device Role / Timing Role: Quad-channel ADC with programmable gain and LVDS output interface enables scalable channel density without increasing digital bus complexity. Use Value: 12-cycle deterministic latency and frame-aligned outputs simplify trigger synchronization across multiple modules; 64-pin QFN allows dense PCB stacking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-channel, 12-bit, high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS6423IRGCT | 80 MSPS max sampling rate; 300 mW lower power (1.05 W total); 1 dB lower SFDR at 170 MHz (82 dBc vs. 81 dBc). | Better suited for cost-sensitive, lower-bandwidth IF sampling where 105 MSPS headroom is unnecessary. | Select when system clock rate and thermal envelope constrain maximum sampling frequency. |
| ADS6444IRGCT | 14-bit resolution, 80 MSPS; higher 74.5 dBFS SINAD but 2× power (2.6 W); pin-compatible with ADS6424IRGCT in same RGC package. | Required for applications demanding >11.5 ENOB, such as high-fidelity spectrum analyzers or radar pulse compression. | Choose only if additional 2-bit resolution justifies 2× power increase and FPGA resource overhead for wider data bus. |
Compared with ADS6424IRGCT, ADS6423IRGCT trades 25 MSPS bandwidth and 1 dB SFDR for 22% lower power, while ADS6444IRGCT adds 2-bit resolution at double the power and identical pinout - making ADS6424IRGCT the optimal balance of speed, dynamic performance, and efficiency for 100+ MSPS IF digitization.
Availability
ADS6424IRGCT is available at Aetrix Electronics and suitable for base-station IF receivers, medical ultrasound front-ends, and automated test equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for ADS6424IRGCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, communications, and medical markets.
The ADS642X family was designed specifically for high-density, multi-channel IF sampling in wireless infrastructure and instrumentation - emphasizing low jitter, LVDS interface scalability, and flexible gain control without external components.
FAQ
What is the maximum sampling rate supported by the ADS6424IRGCT?
The ADS6424IRGCT supports a maximum sampling rate of 105 MSPS, validated across the full industrial temperature range (–40°C to +85°C). At this rate, it maintains 91 dBc SFDR at 10 MHz input and 79 dBc at 170 MHz with 3.5 dB coarse gain enabled. Performance metrics are specified in the SLAS532B datasheet revision December 2013.
Does the ADS6424IRGCT require an external reference voltage?
No, the ADS6424IRGCT includes an internal reference with VREFT = 2.0 V and VREFB = 1.0 V, delivering ±2 mV reference error. It also supports external reference mode via the VCM pin, where external reference common-mode voltage must be 1.45–1.55 V. No external decoupling capacitors are required for either mode.
How many LVDS data pairs does the ADS6424IRGCT use for its serial interface?
The ADS6424IRGCT uses eight LVDS data pairs (DA0–DD1, each with P/M) plus two LVDS clock pairs (DCLKP/DCLKM and FCLKP/FCLKM) in its 2-wire DDR interface. Each of the four ADC channels outputs serialized 12-bit data over two dedicated LVDS pairs, enabling halved data rate versus 1-wire operation.
What is the ADC latency of the ADS6424IRGCT and how is it defined?
The ADS6424IRGCT has a fixed ADC latency of 12 clock cycles from input clock rising edge to valid data at the LVDS outputs, as shown in Figure 1 of the SLAS532B datasheet. This latency is deterministic and independent of interface mode (1-wire/2-wire or SDR/DDR), enabling precise timing alignment in synchronous systems.
Can the ADS6424IRGCT operate with both parallel pin control and serial register programming simultaneously?
Yes, the ADS6424IRGCT supports hybrid configuration where parallel pins (CFG1–CFG4, PDN, SEN) set boot-time defaults and serial registers override specific functions - governed by a priority table in the datasheet. For example, CFG1 defines 2-wire/DDR mode at power-up, while serial register 0x0D bit
ADS6424IRGCT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 105M
- Number of Inputs:
- 4
- Input Type:
- Differential
- Data Interface:
- LVDS - Serial
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 4
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 3V ~ 3.6V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 64-VQFN (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS6424IRGCT FAQ
1.How can I place an order for ADS6424IRGCT through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS6424IRGCT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS6424IRGCT reliable?
The price and inventory of ADS6424IRGCT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6424IRGCT is usually 5 days.
3.What payment methods are accepted for ADS6424IRGCT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6424IRGCT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS6424IRGCT?
ADS6424IRGCT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS6424IRGCT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS6424IRGCT?
For technical support, including ADS6424IRGCT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6424IRGCT requirements.
6.How does Aetrix verify that ADS6424IRGCT is sourced from the original manufacturer or authorized distributors?
All ADS6424IRGCT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6424IRGCT meets industry standards.
7.What is the process for return or replacement of ADS6424IRGCT?
All ADS6424IRGCT units undergo pre-shipment inspection (PSI). If there is an issue with ADS6424IRGCT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS6424IRGCT part is unused and in its original packaging.
Return procedure for ADS6424IRGCT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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