Texas Instruments ADS7890IPFBTG4

Overview

ADS7890IPFBTG4 from Texas Instruments is a 14-bit, 1.25 MSPS successive approximation register (SAR) analog-to-digital converter with integrated 2.5-V reference and pseudo-differential unipolar input (0 V to 2.5 V). It features zero latency, SPI/DSP-compatible serial interface, 77.5 dB SNR at 0.5 MHz input, and operates in Nap mode (10 mW) or full-speed mode (45 mW). It targets high-speed data acquisition in optical networking and spectrum analysis systems.

For engineers reviewing the ADS7890IPFBTG4 datasheet, ADS7890IPFBTG4 pinout, ADS7890IPFBTG4 application, or ADS7890IPFBTG4 equivalent, this page delivers verified technical context, package mapping, real-world timing behavior, and validated alternative options - all grounded in TI's SLAS409 specification document dated December 2003.

Technical Context

The ADS7890IPFBTG4 implements a capacitor-based SAR architecture with inherent sample-and-hold, enabling true zero-latency conversion. Its pseudo-differential input stage accepts +IN (−0.2 V to 2.7 V) and −IN (±200 mV), supporting common-mode noise rejection and ground mismatch compensation without external circuitry.

It supports dual digital interfaces: SPI (CS/SCLK/SDO/BUSY) and DSP (CS/SCLK/FS/SDO/BUSY), both requiring 16 clock cycles per frame. Internal conversion timing is fixed at 365 ns max, with aperture jitter of 20 ps and acquisition time of 187.5 ns - critical for maintaining 77.5 dB SNR at 0.5 MHz input frequency.

Key Specifications

Pinout & Package

ADS7890IPFBTG4 is housed in a 48-pin TQFP package (PFB designation), with exposed thermal pad (not electrically connected). Pin layout separates analog (AGND, +VA, +IN, −IN, REFM, REFIN, REFOUT) and digital (BDGND, +VBD, SDO, BUSY, SCLK, CS, FS, PWD/RST) domains to minimize coupling; AGND and BDGND must be shorted beneath the device.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed SAR ADC applications.

Compared with ADS8325IPFB, ADS7890IPFBTG4 trades 2-bit resolution for 25% higher throughput and integrated reference - reducing component count and simplifying layout. Against ADS7891IPFB, it provides tighter unipolar input optimization and lower input-referred noise in 0–2.5 V range, making it preferable for optical and telecom sensing where signal polarity is fixed.

Availability

ADS7890IPFBTG4 is available at Aetrix Electronics and suitable for optical networking, spectrum analysis, high-speed closed-loop control, and telecom baseband acquisition requiring stable component supply and long-term industrial availability.

Supply support for ADS7890IPFBTG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision data converters and high-speed signal chains.

The ADS7890 belongs to TI's high-speed SAR ADC family designed for applications demanding zero-latency, low-power operation, and robust noise immunity - particularly in optical, test & measurement, and communications infrastructure.

FAQ

What is the maximum input voltage range supported by ADS7890IPFBTG4?

The ADS7890IPFBTG4 supports a pseudo-differential unipolar input range: +IN accepts −0.2 V to (V_REF + 0.2 V) = 2.7 V, while −IN is strictly limited to ±200 mV. The effective input span (+IN − −IN) is 0 V to 2.5 V when using the internal 2.5 V reference. Exceeding these limits risks linearity degradation or damage - confirmed in Absolute Maximum Ratings and Analog Input specifications of SLAS409.

Does ADS7890IPFBTG4 require an external reference, or does it include one?

The ADS7890IPFBTG4 includes a buffered 2.5 V internal reference with 25 ppm/°C drift and 2.5 V ±20 mV tolerance over temperature. When used, REFOUT (pin 2) must be connected to REFIN (pin 1) via 0.1 µF and 1 µF capacitors to AGND. An external reference may be applied to REFIN, but then REFOUT must remain unconnected to REFIN - as explicitly defined in the REFERENCE section of SLAS409.

How does the Nap mode function in ADS7890IPFBTG4, and what power savings does it provide?

Nap mode in ADS7890IPFBTG4 automatically activates after conversion completion and reduces analog supply current to 2–3 mA (typical), cutting power dissipation from 45 mW to ~10 mW. It exits on the 8th SCLK rising edge, enabling deterministic wake-up. This behavior is intrinsic to the device's timing architecture - not software-configurable - and is validated in Timing Requirements and Power Supply sections of SLAS409.

Can ADS7890IPFBTG4 interface with both SPI and DSP controllers?

Yes, ADS7890IPFBTG4 supports two hardware-compatible serial interfaces: SPI (using CS, SCLK, SDO, BUSY) and DSP (using CS, SCLK, FS, SDO, BUSY). Mode selection is determined by signal routing - FS held high enables SPI; FS actively toggled enables DSP. Both use 16-clock frames and MSB-first straight binary format, with identical timing constraints for SCLK, CS, and BUSY - per Figures 1 and 2 in SLAS409.

What is the significance of the −IN pin's ±200 mV range in ADS7890IPFBTG4?

The −IN pin's ±200 mV range in ADS7890IPFBTG4 enables common-mode noise rejection and ground potential mismatch compensation between sensor and ADC. By allowing small differential offsets, it cancels correlated noise without requiring matched external resistors or op-amp circuitry - directly improving system-level SNR in real-world layouts. This capability is specified in the Analog Input section and validated by 60 dB CMRR at 0.5 MHz in SLAS409.