Texas Instruments ADS800U/1K

Overview

ADS800U/1K from Texas Instruments is a 12-bit, 40MHz pipeline analog-to-digital converter with internal reference, wideband track-and-hold (65MHz full-power bandwidth), single +5V supply operation, and differential or single-ended input support - deployed in ultrasound imaging, IF digitization, and high-speed test instrumentation.

For engineers reviewing the ADS800U/1K datasheet, ADS800U/1K pinout, ADS800U/1K application, or ADS800U/1K equivalent, key selection considerations include its 6.5-cycle data latency, ±0.6 LSB typical DNL at 500kHz, 65dBFS SFDR, TTL/HCT-compatible three-state outputs, and SO-28 package thermal resistance of 75°C/W.

Technical Context

The ADS800U/1K implements an 11-stage pipelined architecture with 2-bit quantizers per stage and digital error correction to ensure no missing codes and <±1.0 LSB integral linearity across temperature. Its fully differential track-and-hold accepts 180° out-of-phase inputs with ±1.25V swing around +2.25V common-mode voltage.

Conversion is clocked by a 40MHz CMOS-level signal with strict timing: minimum 12ns high/low pulse width, 2ns rise/fall time, and low jitter critical for maintaining 61–64dB SNR. Output coding is selectable between Straight Offset Binary (SOB) and Binary Two's Complement (BTC) via MSBI pin, with three-state control via OE.

Key Specifications

Pinout & Package

ADS800U/1K is housed in a 28-pin SOIC (SO-28) package with exposed pad not specified; thermal resistance θ_JA = 75°C/W. Pin 15, 17, 20, and 24 are dedicated +VS connections; pins 1, 14, 25, and 28 are GND; dual complementary analog inputs occupy pins 26 and 27.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS800U/1K, ADS802U extends temperature range with tighter gain stability, while AD9220AR trades speed for higher static accuracy and integrated reference - making ADS800U/1K optimal for cost-sensitive, high-throughput IF and imaging systems needing 40MSPS with proven reliability.

Availability

ADS800U/1K is available at Aetrix Electronics and suitable for ultrasound imaging systems, wireless IF receivers, automated test equipment, and high-resolution CCD scanning applications requiring stable component supply and long-term production continuity.

Supply support for ADS800U/1K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of innovation in data converters and signal chain solutions.

The ADS800U/1K belongs to TI's high-speed pipeline ADC product line, engineered for demanding communications, medical imaging, and instrumentation applications where speed, linearity, and low power coexist.

FAQ

What is the maximum recommended clock jitter for ADS800U/1K to maintain 61dB SNR?

ADS800U/1K requires aperture jitter ≤7ps rms to sustain 61dB SNR at 500kHz input. Measured jitter exceeding 10ps rms degrades SNR by ≥3dB due to sampling uncertainty. Clock sources must exhibit sub-1ps period jitter and <2ns edge rates; TI recommends using low-jitter LVDS oscillators or cleaned-up crystal sources with PLLs meeting these specs for ADS800U/1K deployment.

Can ADS800U/1K operate with a single-ended input, and what is the resulting full-scale range?

Yes, ADS800U/1K supports single-ended mode by tying IN (pin 27) to CM (pin 22). This yields a +0.25V to +4.25V full-scale range using internal references. However, even-order harmonics increase above 5MHz input frequency. For time-domain applications like pulse capture where harmonic distortion is less critical than timing fidelity, this configuration reduces external driver complexity versus differential drive.

How does the MSBI pin affect ADS800U/1K output coding, and is it compatible with common FPGA interfaces?

ADS800U/1K MSBI pin selects output coding: logic LOW or floating enables Straight Offset Binary (SOB), where full-scale input = 0xFFF; logic HIGH enables Binary Two's Complement (BTC), inverting B1 (MSB). Both formats are FPGA-compatible - SOB aligns with Xilinx Vivado AXI-Stream defaults, while BTC matches Intel Quartus signed arithmetic blocks. Internal pull-down ensures safe default SOB behavior at power-up.

What is the purpose of the REFT and REFB pins on ADS800U/1K, and can they be driven externally?

REFT (pin 23) and REFB (pin 21) provide access to ADS800U/1K's internal +3.25V and +1.25V reference nodes for external bypassing with 0.1µF capacitors. They may be overridden by external references capable of ≥18mA sink/source, enabling full-scale range adjustment (e.g., ±1.0V differential) or improved gain drift. External references must stay within +1.1V to +3.4V bounds and maintain ≥1.5V difference to ensure proper operation of ADS800U/1K.

Does ADS800U/1K require separate analog and digital ground planes, and how should they be connected?

Yes, ADS800U/1K requires separation of analog (AGND) and digital (DGND) ground domains. Per TI layout guidance, all GND pins (1, 14, 25, 28) must connect directly to a solid analog ground plane - not a split or digital plane. The +VS supply commons tie to this same analog plane. Digital outputs (B1–B12) drive low-capacitance loads locally; no digital ground connection is made to the IC. This minimizes noise coupling and preserves 65dBFS SFDR in ADS800U/1K systems.