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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADS803E/1KG4

Name: ADS803E/1KG4
Brand: Texas Instruments
SKU: ADS803E/1KG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADS803E/1KG4

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 28-SSOP (0.209", 5.30mm Width)

Datasheet:: ADS803E/1KG4.pdf

Description:: IC ADC 12BIT PIPELINED 28SSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

ADS803E/1KG4 from Texas Instruments is a 12-bit, 5 MSPS pipelined analog-to-digital converter optimized for high-dynamic-range signal acquisition in IF/baseband and imaging systems. It delivers 82 dB SFDR at Nyquist, 69 dB SNR, 0.25 LSB DLE, 5 V_p-p input range option with 0.09 LSB_rms input-referred noise, and integrated over-range detection - enabling precision digitization in CCD scanners and test instrumentation.

For engineers reviewing the ADS803E/1KG4 datasheet, ADS803E/1KG4 pinout, ADS803E/1KG4 application, or ADS803E/1KG4 equivalent, key selection criteria include sampling rate vs. SFDR trade-offs, flexible reference configuration (2 V_p-p or 5 V_p-p), CMOS/TTL-compatible 3-state digital outputs, OVR flag timing alignment with pipeline latency, and SSOP-28 thermal performance under industrial temperature range (–40°C to +85°C).

Technical Context

The ADS803E/1KG4 employs a 6-stage pipelined architecture with on-chip track-and-hold, digital error correction, and internal voltage reference selectable between +1 V and +2.5 V. Its 270 MHz track-mode bandwidth and 4 ps_rms aperture jitter support high-fidelity sampling of signals up to 2.48 MHz without significant SNR degradation.

It features programmable input range via SEL/VREF pin strapping, separate VDRV supply for digital output level control (3 V or 5 V logic compatibility), and synchronous 3-state output enable (OE) with 20–40 ns enable/disable timing. The OVR flag is pipeline-synchronized and updates with each conversion result.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	12-bit tested; guarantees monotonicity and no missing codes across full temperature range.
Sampling Rate	5 MSPS maximum; supports real-time digitization of IF signals up to 2.48 MHz with >65 dB SINAD.
SFDR	82 dBFS at f_IN = 2.48 MHz (–1 dBFS); enables clean spectral capture in dense RF environments.
SNR	69 dB at f_IN = 2.48 MHz (–1 dBFS); corresponds to ~11.3 ENOB for high-fidelity waveform reconstruction.
Differential Linearity	±0.25 LSB typical; ensures minimal code-dependent gain error critical for imaging linearity.
Input Referred Noise	0.09 LSB_rms (5 V_p-p range); reduces quantization uncertainty in low-contrast CCD pixel readout.
Data Latency	6 clock cycles; deterministic pipeline delay simplifies timing closure in synchronous FPGA interfaces.

Pinout & Package

ADS803E/1KG4 is housed in a 28-pin SSOP (DB) package with exposed pad not electrically connected. Pin spacing is 0.65 mm, body width 5.3 mm, and thermal resistance θ_JA = 50°C/W. Layout requires separate analog/digital ground tie at package, local 0.1 µF ceramic bypassing per supply pin, and controlled-impedance CLK routing.

Pin/Terminal	Circuit Role	Design Meaning
OVR	Over-range indicator output	Active-HIGH flag synchronized to pipeline output; indicates input exceeding REFT/REFB bounds - used for automatic gain control in front-end amplifiers.
B1–B12	Parallel digital output bits	MSB-first straight offset binary; 3-state controlled by OE; compatible with 3 V or 5 V logic depending on VDRV setting.
CLK	Convert clock input	Rising-edge triggered; requires <2 ns rise/fall time and <4 ps_rms jitter to maintain 69 dB SNR performance.
OE	Output enable	Active-LOW; enables/disables all B1–B12 outputs with 20–40 ns enable and 2–10 ns disable propagation.
+VS	Analog supply	+4.7 V to +5.3 V; powers analog core, reference, and T/H - must be decoupled independently from digital supplies.
VDRV	Digital driver supply	Independent 3 V or 5 V rail; sets output voltage levels without affecting analog section - enables mixed-voltage system interfacing.
SEL / VREF / REFT / REFB / CM	Reference configuration network	Pin-strapped to select 2 V_p-p (SEL→VREF) or 5 V_p-p (SEL→GND) full-scale range; REFT/REFB provide buffered top/bottom references for external biasing.
IN / IN	Differential analog inputs	Accept single-ended or differential drive; common-mode voltage set to +2.5 V by internal ladder midpoint - requires <20 pF input capacitance matching.

Key Features

Feature	Design Value
Flexible input range selection	Hardware-configurable 2 V_p-p (optimized SFDR) or 5 V_p-p (minimized input-referred noise) via SEL/VREF strapping - no external components required.
Pipeline latency compensation	Fixed 6-cycle data latency with synchronized OVR flag - enables deterministic timing in FPGA-based digital downconverters and real-time histogram engines.
Low-jitter aperture performance	4 ps_rms aperture jitter and 270 MHz track-bandwidth preserve SNR up to Nyquist - critical for undersampling architectures in spectrum analyzers.
Isolated digital I/O supply	VDRV pin allows independent 3 V or 5 V digital rail - eliminates need for level translators when interfacing to modern low-voltage FPGAs or ASICs.
Integrated over-range monitoring	OVR flag provides cycle-accurate saturation detection - used to trigger automatic gain reduction in CCD scanner front-ends before clipping occurs.

Applications

CCD Imaging Scanners	Test Instrumentation
Use Scenario: High-speed line-scan digitization of photodiode array outputs in document scanners and industrial inspection systems. IC Role / Device Role / Timing Role: Primary ADC capturing analog pixel voltages at 5 MSPS with sub-LSB linearity to preserve spatial contrast and edge fidelity. Use Value: 0.09 LSB_rms input-referred noise and ±0.25 LSB DLE ensure accurate grayscale reproduction across 4096 intensity levels without banding artifacts.	Use Scenario: Digitizing calibrated sensor outputs and stimulus waveforms in automated test equipment (ATE) and benchtop oscilloscopes. IC Role / Device Role / Timing Role: High-SFDR acquisition channel for dynamic signal analysis, supporting FFT-based distortion measurement up to 2.48 MHz. Use Value: 82 dB SFDR and 69 dB SNR enable reliable detection of –74 dBc intermodulation products in two-tone tests - meeting IEEE 1057 compliance thresholds.
IF Digitization	Medical Ultrasound Receivers
Use Scenario: Direct sampling of 70 MHz IF signals in software-defined radio (SDR) receivers using undersampling techniques. IC Role / Device Role / Timing Role: Bandpass-sampled ADC operating at 5 MSPS with precise aperture jitter control to minimize aliasing-induced SNR loss. Use Value: 4 ps_rms aperture jitter limits SNR degradation to <0.5 dB at 70 MHz center frequency - preserving dynamic range for weak signal detection.	Use Scenario: Beamformed echo signal digitization in portable ultrasound systems requiring low power and high SNR. IC Role / Device Role / Timing Role: Channel ADC in multi-channel receive path, synchronized to beam-steering clocks with deterministic 6-cycle latency. Use Value: 115 mW power consumption at 5 MSPS and 69 dB SNR allow integration into battery-powered handheld units without thermal throttling.

CCD Imaging Scanners

Test Instrumentation

Use Scenario: High-speed line-scan digitization of photodiode array outputs in document scanners and industrial inspection systems.

IC Role / Device Role / Timing Role: Primary ADC capturing analog pixel voltages at 5 MSPS with sub-LSB linearity to preserve spatial contrast and edge fidelity.

Use Value: 0.09 LSB_rms input-referred noise and ±0.25 LSB DLE ensure accurate grayscale reproduction across 4096 intensity levels without banding artifacts.

Use Scenario: Digitizing calibrated sensor outputs and stimulus waveforms in automated test equipment (ATE) and benchtop oscilloscopes.

IC Role / Device Role / Timing Role: High-SFDR acquisition channel for dynamic signal analysis, supporting FFT-based distortion measurement up to 2.48 MHz.

Use Value: 82 dB SFDR and 69 dB SNR enable reliable detection of –74 dBc intermodulation products in two-tone tests - meeting IEEE 1057 compliance thresholds.

IF Digitization

Medical Ultrasound Receivers

Use Scenario: Direct sampling of 70 MHz IF signals in software-defined radio (SDR) receivers using undersampling techniques.

IC Role / Device Role / Timing Role: Bandpass-sampled ADC operating at 5 MSPS with precise aperture jitter control to minimize aliasing-induced SNR loss.

Use Value: 4 ps_rms aperture jitter limits SNR degradation to <0.5 dB at 70 MHz center frequency - preserving dynamic range for weak signal detection.

Use Scenario: Beamformed echo signal digitization in portable ultrasound systems requiring low power and high SNR.

IC Role / Device Role / Timing Role: Channel ADC in multi-channel receive path, synchronized to beam-steering clocks with deterministic 6-cycle latency.

Use Value: 115 mW power consumption at 5 MSPS and 69 dB SNR allow integration into battery-powered handheld units without thermal throttling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, high-dynamic-range ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS804E	10 MSPS max sampling rate; identical pinout and reference architecture; higher power (145 mW) and slightly lower SFDR (80 dB at Nyquist)	Better suited for wider instantaneous bandwidth requirements where 5–10 MSPS trade-off is acceptable	Select ADS804E only if system requires >5 MSPS while retaining same PCB layout and firmware interface.
ADS805E	20 MSPS max sampling rate; same SSOP-28 package; higher power (175 mW); SFDR degrades to 78 dB at Nyquist due to increased clock sensitivity	Targeted at wideband communications test gear needing >10 MSPS with moderate SFDR tolerance	Choose ADS805E when sampling bandwidth exceeds 10 MSPS and SNR >67 dB remains sufficient for application.

Compared with ADS803E/1KG4, ADS804E offers +5 MSPS headroom at modest SFDR cost and identical footprint, while ADS805E extends bandwidth further but sacrifices 4 dB SFDR and increases power by 52% - making ADS803E/1KG4 optimal for 5 MSPS applications prioritizing spectral purity and power efficiency.

Availability

ADS803E/1KG4 is available at Aetrix Electronics and suitable for CCD imaging scanners, IF digitization subsystems, and automated test instrumentation requiring stable component supply across extended product lifecycles.

Supply support for ADS803E/1KG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters with over 40 years of precision ADC innovation.

The ADS803E/1KG4 belongs to TI's high-speed pipeline ADC family designed specifically for demanding communications, medical imaging, and instrumentation applications where SFDR, SNR, and deterministic latency are critical system-level constraints.

FAQ

What is the absolute maximum input voltage range for ADS803E/1KG4?

The absolute maximum analog input voltage range for ADS803E/1KG4 is (–0.3 V) to (+V_S + 0.3 V), where V_S is the analog supply voltage (typically +5 V). Exceeding this range risks permanent damage. The specified operational input range is 0 V to 5 V (single-ended) or ±2.5 V (differential), with common-mode voltage fixed at +2.5 V unless externally adjusted. Always observe the 20 pF input capacitance limit and avoid driving beyond REFT/REFB boundaries to prevent OVR flag misalignment.

Does ADS803E/1KG4 support external reference operation?

Yes, ADS803E/1KG4 supports external reference operation. To enable it, connect the SEL pin to +V_S, which disables the internal reference and disconnects the VREF pin from the internal buffer. The VREF pin must then be driven by an external reference source (0.5 V to 2.5 V). External reference bypassing must mirror the internal scheme: 0.1 µF ceramic + 10 µF bulk capacitor per REFT/REFB node. This mode improves DC accuracy in applications where external references offer superior drift (<10 ppm/°C) and initial tolerance (<0.1%).

How is the OVR flag synchronized with data output in ADS803E/1KG4?

The OVR flag in ADS803E/1KG4 is pipeline-synchronized and updates concurrently with the B1–B12 data bits after the fixed 6-clock-cycle latency. It reflects the over-range condition of the same sample being output - not the currently sampled value. For example, when conversion N completes, OVR indicates whether sample N exceeded REFT/REFB bounds. This alignment allows direct use of OVR with MSB in FPGA logic (e.g., Figure 11 in SBAS074B) to detect under/over-range events without additional timing compensation.

Can ADS803E/1KG4 interface directly with 3.3 V logic systems?

Yes, ADS803E/1KG4 can interface directly with 3.3 V logic systems using the VDRV pin. Set VDRV = 3.3 V while maintaining +V_S = 5 V for the analog section. This configures the B1–B12 outputs to swing between 0.1 V (low) and 2.4 V (high) at I_OH = 0.5 mA, meeting 3.3 V TTL/CMOS input thresholds. Ensure OE is actively controlled and capacitive load per data line stays ≤15 pF. Series termination resistors (100–200 Ω) are recommended to suppress reflections and reduce digital switching noise coupling into analog sections.

What is the recommended power supply decoupling for ADS803E/1KG4?

The recommended power supply decoupling for ADS803E/1KG4 requires per-pin 0.1 µF X7R ceramic capacitors placed within 2 mm of each +V_S (pins 16, 27) and VDRV (pin 28), plus a shared 2.2 µF tantalum or 10 µF aluminum electrolytic capacitor near the device. Analog and digital grounds must be tied together only at the package (pins 17, 24, 26) and connected to a solid analog ground plane. Avoid splitting ground planes or routing digital traces near analog supply lines - noise on +V_S directly degrades SNR by up to 20 dB if ripple exceeds 10 mV_pp.

ADS803E/1KG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 28-SSOP (0.209", 5.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Number of Bits:: 12

Sampling Rate (Per Second):: 5M

Number of Inputs:: 1

Input Type:: Differential, Single Ended

Data Interface:: Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 5V

Voltage - Supply, Digital:: 5V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 28-SSOP

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADS803E/1KG4 FAQ

1.How can I place an order for ADS803E/1KG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADS803E/1KG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADS803E/1KG4 reliable?

The price and inventory of ADS803E/1KG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS803E/1KG4 is usually 5 days.

3.What payment methods are accepted for ADS803E/1KG4?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS803E/1KG4 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADS803E/1KG4?

ADS803E/1KG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADS803E/1KG4 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADS803E/1KG4?

For technical support, including ADS803E/1KG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS803E/1KG4 requirements.

6.How does Aetrix verify that ADS803E/1KG4 is sourced from the original manufacturer or authorized distributors?

All ADS803E/1KG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS803E/1KG4 meets industry standards.

7.What is the process for return or replacement of ADS803E/1KG4?

All ADS803E/1KG4 units undergo pre-shipment inspection (PSI). If there is an issue with ADS803E/1KG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADS803E/1KG4 part is unused and in its original packaging.

Return procedure for ADS803E/1KG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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