Texas Instruments ADS803IDBRHE
- Part No.:
- ADS803IDBRHE
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- -
- Datasheet:
-
ADS803IDBRHE.pdf
- Description:
- ANALOG AUTOMOTIVE
- Quantity:
- Payment:

- Shipping:

Inventory:7,551
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADS803IDBRHE from Texas Instruments is a 12-bit, 5-MSPS pipelined analog-to-digital converter with internal reference, 82 dB SFDR at Nyquist, 69 dB SNR, and 0.25 LSB DLE. It operates with flexible input ranges (2 VP-P or 5 VP-P) and includes an over-range indicator flag for front-end gain control in IF digitization systems.
For engineers reviewing the ADS803IDBRHE datasheet, ADS803IDBRHE pinout, ADS803IDBRHE application, or ADS803IDBRHE equivalent, key selection considerations include sampling rate vs. dynamic performance trade-offs, input range programmability, aperture jitter sensitivity (<4 ps rms), CMOS/TTL-compatible 3-state outputs, and SSOP-28 package compatibility with ADS804/ADS805 layouts.
Technical Context
The ADS803IDBRHE employs a high-bandwidth track-and-hold with 270 MHz –3 dBFS input bandwidth to minimize harmonic distortion and jitter, enabling high-fidelity digitization up to Nyquist. Its digital error-correction logic ensures ±0.25 LSB typical differential linearity across temperature.
It supports single-ended or differential analog inputs, programmable full-scale range via VREF/SEL pin strapping (2 VP-P, 5 VP-P, or intermediate), and dual-supply operation: +5 V analog supply (+VS) and independent 3–5 V digital driver voltage (VDRV) for mixed-voltage interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit tested - guarantees monotonic output and no missing codes over full temperature range. |
| Sampling Rate | 5 MSPS maximum - enables real-time digitization of IF signals up to 2.48 MHz with >65 dB SINAD. |
| SFDR | 82 dBFS at 2.48 MHz input - suppresses largest spurious tone by 82 dB below full-scale, critical for spectral purity in communications receivers. |
| SNR | 69 dB at 2.48 MHz - delivers 11.2 effective bits (ENOB) for high-fidelity baseband reconstruction. |
| Differential Linearity | ±0.25 LSB typical - ensures minimal code-width variation, essential for low-distortion imaging and test instrumentation linearity. |
| Input Referred Noise | 0.09 LSBrms (5 VP-P range) - enables superior dynamic range in CCD scanners where quantization noise dominates system floor. |
| Aperture Jitter | 4 ps rms - limits SNR degradation to <0.5 dB at 2.48 MHz, requiring low-jitter clock sources for optimal performance. |
| Power Dissipation | 115 mW at 5 MSPS - balances speed and thermal load in space-constrained embedded data acquisition modules. |
Pinout & Package
ADS803IDBRHE is housed in a 28-pin SSOP (Shrink Small Outline Package) with 0.65 mm lead pitch, RoHS-compliant NIPDAU finish, and MSL Level-2 moisture sensitivity rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OVR | Over-range indicator output | Active-high flag signaling input voltage exceeding selected full-scale range; synchronized to pipeline latency (6 clock cycles). |
| B1–B12 | Parallel digital output bits | MSB-to-LSB straight offset binary format; 3-state controlled by OE; CMOS/TTL compatible with VDRV-supplied logic levels. |
| CLK | Convert clock input | Rising-edge triggered; requires 50% duty cycle, <2 ns rise/fall time, and minimal jitter to preserve SNR. |
| OE | Output enable | Active-low control for 3-state outputs; 20–40 ns enable/disable timing ensures clean bus sharing without contention. |
| +VS | Analog supply | +4.7 V to +5.3 V; powers analog core, reference, and track-and-hold; must be decoupled per Figure 12. |
| SEL | Input range select | Pin-strapped to VREF or GND to configure 2 VP-P (SEL=VREF) or 5 VP-P (SEL=GND) full-scale span. |
| VREF | Reference voltage select | Outputs +1 V or +2.5 V internal reference; sets full-scale span = 2 × VREF; can be overridden by external reference when SEL = +VS. |
| REFT / REFB | Top/bottom reference outputs | Provide buffered +3 V / +2 V (2 VP-P mode) or +4.5 V / +0.5 V (5 VP-P mode); require 0.1 µF + 10 µF bypassing to minimize clock feedthrough. |
| CM | Common-mode voltage node | High-impedance midpoint (~+2.5 V) for biasing differential inputs; not buffered-external resistive divider recommended if loaded. |
| IN / IN | Differential analog inputs | Accept single-ended or differential signals; input capacitance 20 pF; track-mode bandwidth 270 MHz supports wideband IF sampling. |
| VDRV | Digital driver supply | Independent 3–5 V supply for output drivers-enables direct interface to 3.3 V or 5 V logic without level shifters. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable input range | 2 VP-P (best SFDR) or 5 VP-P (lowest input-referred noise: 0.09 LSBrms) via SEL/VREF pin strapping-no external components required. |
| Integrated over-range detection | OVR flag provides real-time out-of-range monitoring with pipeline-synchronized timing-enables automatic gain adjustment in closed-loop front ends. |
| Digital error correction | Compensates for capacitor mismatch in pipeline stages-guarantees ±0.25 LSB DLE and monotonicity across –40°C to +85°C. |
| Independent digital supply (VDRV) | Separates digital I/O noise from analog core-allows simultaneous +5 V analog operation and 3.3 V logic interfacing without signal integrity compromise. |
| High-bandwidth track-and-hold | 270 MHz –3 dBFS bandwidth minimizes harmonic distortion and preserves SNR even with fast-rising IF transients. |
Applications
| IF Digitization | CCD Imaging Scanners |
|---|---|
Use Scenario: Digitizing 70–140 MHz IF signals in software-defined radio receivers after bandpass filtering and gain staging. IC Role / Device Role / Timing Role: High-speed ADC capturing instantaneous amplitude/phase for digital downconversion; clocked at 5 MSPS with <4 ps jitter. Use Value: 82 dB SFDR prevents adjacent-channel interference masking weak signals; 69 dB SNR enables 16-QAM demodulation fidelity. | Use Scenario: Converting pixel charge outputs from linear CCD arrays in industrial inspection systems operating at 10–20 kHz line rates. IC Role / Device Role / Timing Role: Precision digitizer for analog video output; uses 5 VP-P range to maximize dynamic range against CCD dark current noise. Use Value: 0.09 LSBrms input-referred noise resolves sub-LSB grayscale variations; ±0.25 LSB DLE preserves edge sharpness in defect detection. |
| Test Instrumentation | Medical Ultrasound Beamforming |
Use Scenario: Embedded digitizer in portable oscilloscopes capturing transient waveforms up to 2.5 MHz bandwidth with >65 dB SINAD. IC Role / Device Role / Timing Role: Core ADC in acquisition path; leverages internal reference for stable full-scale calibration across temperature. Use Value: ±1 LSB INL and 68 dB SINAD ensure accurate amplitude measurement; 115 mW power enables fanless thermal design. | Use Scenario: Channel ADC in ultrasound receive beamformer processing RF echoes from 2–10 MHz transducers. IC Role / Device Role / Timing Role: High-linearity digitizer for time-gain compensated analog beamformed signals prior to digital beamforming. Use Value: Low DLE (±0.25 LSB) prevents spatial distortion in B-mode images; over-range flag triggers TGC attenuation before saturation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed, medium-resolution ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS804E | 10 MSPS sampling rate; identical pinout and architecture; higher power (145 mW); same SSOP-28 package. | Better suited for wider IF bandwidths (>3 MHz) but trades off SNR (67 dB) and SFDR (79 dB) at full speed. | Select ADS804E only when 10 MSPS is mandatory and system clock jitter can be tightly controlled. |
| ADS805E | 20 MSPS sampling rate; same pinout; higher power (175 mW); reduced SFDR (76 dB) and SNR (65 dB) at Nyquist. | Targeted at undersampling applications above 5 MHz; requires external clock conditioning to maintain aperture jitter <2 ps. | Choose ADS805E for direct RF sampling above 10 MHz where aliasing is managed digitally-not for baseband or narrowband IF. |
Compared with ADS804E and ADS805E, the ADS803IDBRHE delivers optimal balance of 5 MSPS throughput, 82 dB SFDR, and 115 mW power-making it preferred for cost-sensitive, thermally constrained IF digitizers where spectral purity outweighs raw speed.
Availability
ADS803IDBRHE is available at Aetrix Electronics and suitable for IF digitization, CCD imaging scanners, test instrumentation, medical ultrasound beamforming, and industrial data acquisition requiring stable component supply and long-term obsolescence management.
Supply support for ADS803IDBRHE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital signal technologies, with decades of leadership in precision data converters.
The ADS803IDBRHE belongs to TI's high-speed pipeline ADC product line, designed specifically for demanding communications, imaging, and instrumentation applications requiring high dynamic range at moderate sampling rates.
FAQ
What is the maximum sampling rate supported by the ADS803IDBRHE?
The ADS803IDBRHE supports a maximum sampling rate of 5 million samples per second (5 MSPS). This is confirmed in the Electrical Characteristics table under "Conversion Characteristics" with a typical value of 5 MHz and minimum of 10 kSPS. Operation beyond 5 MSPS is not characterized and may degrade SFDR, SNR, or cause timing violations in the pipeline architecture.
Does the ADS803IDBRHE include an internal voltage reference?
Yes, the ADS803IDBRHE integrates a bandgap-based voltage reference that can be configured to output either +1 V or +2.5 V at the VREF pin, depending on the SEL pin connection. This internal reference directly determines the full-scale input range (FSR = 2 × VREF), enabling 2 VP-P or 5 VP-P operation without external components.
How does the OVR (Over-Range) pin function on the ADS803IDBRHE?
The OVR pin on the ADS803IDBRHE is an active-high digital output that asserts HIGH whenever the analog input voltage exceeds the selected full-scale range-either above REFT or below REFB. It updates synchronously with the 6-clock-cycle pipeline latency and remains asserted until the next valid conversion completes within range. This allows real-time gain control in front-end amplifiers.
Can the ADS803IDBRHE interface directly with 3.3 V logic systems?
Yes, the ADS803IDBRHE can interface directly with 3.3 V logic via its dedicated VDRV pin. By supplying 3.3 V to VDRV while maintaining +5 V on +VS, the digital outputs (B1–B12, OVR) swing to 3.3 V–compatible levels. The datasheet specifies CMOS/TTL compatibility and lists high/low output voltages validated at IOH = 0.5 mA and IOL = 1.6 mA under this configuration.
What package type is used for the ADS803IDBRHE?
The ADS803IDBRHE is packaged in a 28-pin SSOP (Shrink Small Outline Package) with DB package drawing, 0.65 mm lead pitch, and RoHS-compliant NIPDAU surface finish. It carries the orderable marking "ADS803E" and is rated for operation from –40°C to +85°C with MSL Level-2 (260°C, 1 year) handling requirements.
ADS803IDBRHE Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Number of Bits:
- -
- Sampling Rate (Per Second):
- -
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- -
- Configuration:
- -
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- -
- Architecture:
- -
- Reference Type:
- -
- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
- -
- Operating Temperature:
- -
- Supplier Device Package:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
ADS803IDBRHE FAQ
1.How can I place an order for ADS803IDBRHE through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS803IDBRHE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS803IDBRHE reliable?
The price and inventory of ADS803IDBRHE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS803IDBRHE is usually 5 days.
3.What payment methods are accepted for ADS803IDBRHE?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS803IDBRHE transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS803IDBRHE?
ADS803IDBRHE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS803IDBRHE order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS803IDBRHE?
For technical support, including ADS803IDBRHE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS803IDBRHE requirements.
6.How does Aetrix verify that ADS803IDBRHE is sourced from the original manufacturer or authorized distributors?
All ADS803IDBRHE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS803IDBRHE meets industry standards.
7.What is the process for return or replacement of ADS803IDBRHE?
All ADS803IDBRHE units undergo pre-shipment inspection (PSI). If there is an issue with ADS803IDBRHE, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS803IDBRHE part is unused and in its original packaging.
Return procedure for ADS803IDBRHE:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADS803IDBRHE Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

