Texas Instruments ADS8900BRGET

Overview

ADS8900BRGET from Texas Instruments is a 20-bit, 1-MSPS successive-approximation-register (SAR) analog-to-digital converter with integrated reference buffer and low-dropout regulator (LDO), designed for high-precision, low-noise data acquisition in unipolar differential input configurations up to ±5 V. It delivers 104.5 dB SNR and –125 dB THD at 2 kHz, supports 22 MHz enhanced-SPI interface, and operates across –40°C to +125°C.

For engineers reviewing the ADS8900BRGET datasheet, ADS8900BRGET pinout, ADS8900BRGET application, or ADS8900BRGET equivalent, this page provides verified technical context, validated pin functions, confirmed AC/DC performance metrics, real-world use cases in test & measurement and medical imaging, and two rigorously cross-checked alternative parts with documented functional differences.

Technical Context

The ADS8900BRGET implements a charge-redistribution SAR architecture with internal clocking, enabling true no-latency output at 1 MSPS while maintaining 20-bit no-missing-codes performance. Its integrated LDO accepts single-supply RVDD (3–5.5 V) and generates stable internal bias, eliminating external regulators.

It features TI's enhanced-SPI interface-backward-compatible with standard SPI-reducing required SCLK frequency to 22 MHz at full throughput and supporting configurable parity bits for host-side data validation. The reference buffer accepts 2.5–5 V external VREF and maintains <±250 µV offset with 10–22 µF decoupling.

Key Specifications

Pinout & Package

The ADS8900BRGET is housed in a 4 mm × 4 mm, 24-pin VQFN package (RGE) with exposed thermal pad connected to GND. Pin functions are validated per TI SBAS728B Rev. May 2026.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, high-precision SAR ADC applications.

Compared with ADS8900BRGET, ADS8910BRGET trades 2-bit resolution and tighter linearity for lower cost and identical integration, while AD7960BCPZ-RL7 delivers higher speed at the expense of increased system complexity, external component dependencies, and absence of built-in data integrity features.

Availability

ADS8900BRGET is available at Aetrix Electronics and suitable for test and measurement equipment, medical imaging subsystems, and high-precision industrial data acquisition requiring stable component supply, long-term lifecycle assurance, and guaranteed lot traceability.

Supply support for ADS8900BRGET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision data converters and industrial-grade IC design.

The ADS890xB family was engineered specifically for high-fidelity, low-power, single-supply data acquisition in space-constrained, thermally demanding applications-emphasizing integration, reliability, and ease of FPGA/MCU interfacing.

FAQ

What is the maximum sample rate supported by the ADS8900BRGET?

The ADS8900BRGET supports a maximum sample rate of 1 million samples per second (1 MSPS) with no latency output and guaranteed 20-bit performance. This is achieved using its internal clock and charge-redistribution SAR architecture, with conversion time specified at 670 ns maximum. The device maintains full AC/DC specifications-including 104.5 dB SNR and ±1 ppm INL-at this rate across the full –40°C to +125°C operating range.

Does the ADS8900BRGET require an external reference voltage?

Yes, the ADS8900BRGET requires an external reference voltage applied to the REFIN pin, within the range of 2.5 V to 5 V. It does not include an internal reference; instead, it integrates a high-accuracy reference buffer (REFBUFOUT) that conditions and stabilizes the external reference. The buffer supports burst-mode acquisition and exhibits <±250 µV offset at 25°C, with 10–22 µF external decoupling recommended for optimal performance.

How does the enhanced-SPI interface of the ADS8900BRGET differ from standard SPI?

The enhanced-SPI interface of the ADS8900BRGET reduces the required SCLK frequency to 22 MHz at 1 MSPS-versus 70 MHz for standard SPI-by using multi-bit parallel data transfer (SDO-0 through SDO-3) and optimized framing. It remains fully backward-compatible with standard SPI controllers but adds configurable parity output and flexible strobe signaling via the RVS pin, simplifying timing closure and improving data integrity in FPGA- and DSP-based systems.

Can the ADS8900BRGET operate from a single supply rail?

Yes, the ADS8900BRGET can operate from a single 3–5.5 V supply on the RVDD pin thanks to its integrated low-dropout regulator (LDO). The LDO powers internal analog circuitry and reference buffer, eliminating the need for a separate analog supply. Digital interface (DVDD) may be supplied independently at 1.65–5.5 V, but co-location with RVDD is supported and commonly used to simplify power design.

What is the purpose of the DECAP pins on the ADS8900BRGET?

The DECAP pins (13 and 14) on the ADS8900BRGET connect to the internal LDO output and must be decoupled to GND with a 1 µF ceramic capacitor. This capacitor stabilizes the LDO's output voltage, suppresses switching noise, and ensures clean internal biasing-directly impacting SNR, THD, and overall conversion accuracy. TI specifies tPU_LDO = 1 ms with this capacitor, confirming its critical role in power-up sequencing and steady-state performance.