Texas Instruments ADS8910BRGER

Overview

ADS8910BRGER from Texas Instruments is an 18-bit, 1-MSPS successive approximation register (SAR) analog-to-digital converter with integrated reference buffer and low-dropout regulator. It delivers ±0.5-LSB INL, 102.5-dB SNR, and operates from a single 1.65–5.5-V DVDD supply while supporting 2.5–5-V external reference inputs. It targets high-precision data acquisition in test equipment and medical imaging systems.

For engineers reviewing the ADS8910BRGER datasheet, ADS8910BRGER pinout, ADS8910BRGER application, or ADS8910BRGER equivalent, key selection criteria include its 20-MHz enhanced-SPI interface timing at full throughput, integrated LDO enabling single-supply operation, and guaranteed 18-bit no-missing-codes performance across –40°C to +125°C.

Technical Context

The ADS8910BRGER implements a SAR architecture with internal reference buffer and integrated LDO, eliminating need for external voltage regulation. Its enhanced-SPI interface supports configurable parity output and operates at 20 MHz SCLK for 1-MSPS conversion, reducing clocking complexity versus standard SPI.

It uses differential unipolar input range of ±VREF with common-mode voltage centered at VREF/2, and features quiet-time acquisition (30 ns), 2-ps RMS aperture jitter, and 23-MHz small-signal bandwidth - all optimized for high-fidelity signal capture in demanding measurement applications.

Key Specifications

Pinout & Package

The ADS8910BRGER is housed in a 24-pin VQFN package (4 mm × 4 mm, RGE suffix) with exposed thermal pad connected to GND. Pin functions are validated per TI SBAS707B Rev B datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-precision SAR ADC applications.

Compared with ADS8920BRGER and AD7606C-18BSTZ, the ADS8910BRGER uniquely combines 18-bit precision, integrated LDO, and enhanced-SPI in a compact VQFN - reducing total solution size and simplifying clock/data routing in FPGA- or SoC-based systems.

Availability

ADS8910BRGER is available at Aetrix Electronics and suitable for test and measurement equipment, medical imaging front-ends, and high-precision data acquisition requiring stable component supply across extended temperature ranges.

Supply support for ADS8910BRGER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision data converters and industrial-grade ICs.

The ADS891xB family was designed for high-speed, high-accuracy data acquisition in demanding environments - delivering 18-bit SAR performance with integrated power and reference management to simplify system design.

FAQ

What is the maximum sample rate supported by the ADS8910BRGER?

The ADS8910BRGER supports a maximum sample rate of 1 million samples per second (1-MSPS) with zero-latency output. This throughput is fully specified across the operating temperature range of –40°C to +125°C and is achieved using the enhanced-SPI interface with a 20-MHz SCLK. The device maintains full 18-bit performance, including ±0.5-LSB INL and 102.5-dB SNR, at this rate. ADS8910BRGER's architecture ensures deterministic timing without pipeline delay, making it suitable for real-time control loops and burst-mode acquisition.

Does the ADS8910BRGER require an external reference voltage?

The ADS8910BRGER supports both internal and external reference configurations. It includes an integrated low-droop reference buffer that can be used with an external 2.5–5-V reference applied to the REFIN pin. Alternatively, the internal reference buffer may be bypassed to accept a precision external reference directly. The REFBUFOUT pins (5 and 7) are shorted externally and serve as either the buffered output or external reference input depending on configuration. No external reference is mandatory - the device operates with external reference only when higher accuracy or specific voltage scaling is required.

What power supply rails does the ADS8910BRGER require?

The ADS8910BRGER requires two independent supply rails: RVDD (analog supply, 3–5.5 V) and DVDD (digital interface supply, 1.65–5.5 V). An internal LDO generates a regulated 2.85-V supply for the reference buffer from the DECAP pins (13 and 14), which must be decoupled with a 1-µF ceramic capacitor. The device does not require separate AVDD/DVDD rails beyond RVDD and DVDD - the integrated LDO eliminates need for an external analog reference supply. Proper decoupling of both RVDD and DVDD with 100-nF ceramics is essential to maintain specified SNR and THD performance.

How does the enhanced-SPI interface of the ADS8910BRGER differ from standard SPI?

The ADS8910BRGER's enhanced-SPI interface differs from standard SPI by supporting a 4-bit parallel SDO bus (SDO-0 to SDO-3) and configurable parity output, enabling higher effective throughput at lower clock frequencies. At 1-MSPS, it operates with a 20-MHz SCLK - significantly lower than the ~70-MHz clock needed for equivalent throughput using standard SPI. It also provides RVS as a strobe output synchronized to data valid windows, simplifying timing capture in FPGA or ASIC receivers. Unlike standard SPI, enhanced-SPI allows deterministic read timing without requiring complex clock domain crossing logic.

Is the ADS8910BRGER pin-compatible with other devices in the ADS891xB family?

Yes, the ADS8910BRGER is pin-compatible with the ADS8912BRGER (500-kSPS) and ADS8914BRGER (250-kSPS) within the ADS891xB family. All share the identical 24-pin VQFN (RGE) package, identical pin functions, and compatible enhanced-SPI interface. This allows hardware reuse across performance tiers - for example, a single PCB layout can support 1-MSPS, 500-kSPS, or 250-kSPS variants via firmware configuration and BOM change. However, performance specifications (e.g., power consumption, noise, and timing) scale with throughput, so system-level validation is required when substituting across speed grades.