Texas Instruments ADS900E
- Part No.:
- ADS900E
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 28-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
ADS900E.pdf
- Description:
- IC ADC 10BIT PIPELINED 28SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADS900E from Texas Instruments is a 10-bit, 20MHz pipelined analog-to-digital converter (ADC) with internal reference, single-ended input range of +1.0V to +2.0V, wideband track-and-hold (350MHz small-signal bandwidth), and SSOP-28 package. It delivers 49dB SNR at 500kHz input and supports portable instrumentation, cable modems, and set-top boxes.
For engineers reviewing the ADS900E datasheet, ADS900E pinout, ADS900E application, or ADS900E equivalent, this page provides verified technical context, real-world design meaning for key specs, validated pin functions, confirmed alternative parts with functional differences, and supply support for industrial embedded and communications hardware development.
Technical Context
The ADS900E implements a 9-stage pipelined architecture with 2-bit quantizers per stage and digital error correction to guarantee no missing codes and ±0.7LSB differential linearity at 500kHz. Its internal resistor ladder establishes +1.25V (REFB) and +1.75V (REFT) references, yielding a +1.5V common-mode voltage (CM) at Pin 26.
It uses a non-overlapping two-phase internal clock for track-and-hold operation, supports straight offset binary output coding, and features dedicated LVDD (Pin 2) for independent digital output driver supply control. Aperture jitter is specified at 7ps rms, directly limiting SNR in high-frequency sampling applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 10-bit - guarantees 1024 distinct output codes with guaranteed no missing codes across full temperature range. |
| Sampling Rate | 20MSPS - enables digitization of IF signals up to 10MHz Nyquist frequency in communications receivers. |
| Analog Input Range | +1.0V to +2.0V single-ended - defines usable DC-coupled input swing centered at +1.5V CM, compatible with op-amps like OPA680. |
| SNR @ 500kHz | 49dB - corresponds to ~8.2 effective bits; sets dynamic range limit for baseband signal acquisition in test equipment. |
| Spurious-Free Dynamic Range | 53dBFS @ 500kHz - determines largest spurious tone amplitude relative to full-scale signal, critical for spectral purity in cable modem front-ends. |
| Power Dissipation | 52mW @ +3V - enables thermal management in compact portable instrumentation without forced cooling. |
| Aperture Jitter | 7ps rms - limits theoretical SNR to ~58dB at 10MHz input; requires low-jitter clock source for optimal performance. |
Pinout & Package
ADS900E is housed in a 28-pin SSOP (DB) package with 0.635mm pitch, moisture sensitivity level MSL-2 (260°C peak reflow), and RoHS-compliant NiPdAu lead finish. Thermal resistance θJA is 89°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 18, 28 | +VS | Analog supply input - must be decoupled with 0.1µF ceramic capacitors close to each pin; all three pins connect internally to same analog rail. |
| 2 | LVDD | Digital output driver supply - independently adjustable to set VOH/VOL levels; recommended at +3V for TTL/HCT compatibility. |
| 3–12 | Bit 10 to Bit 1 | 10-bit parallel data outputs (D0–D9, LSB to MSB) - straight offset binary coding; 5-cycle latency from CLK edge to valid data. |
| 13, 14, 19, 20 | GND | Analog ground - all four pins must be connected to low-impedance analog ground plane; no separation into AGND/DGND required. |
| 15 | CLK | Convert clock input - accepts 3V/5V CMOS logic; 50% duty cycle and ≤2ns edge rates recommended for 20MSPS operation. |
| 16 | OE | Output enable (active low) - drives outputs to high-impedance when high; internal 50kΩ pull-down ensures default active state. |
| 17 | Pwrdn | Power-down control (active high) - reduces supply current by ~70%; outputs enter 3-state and require 5 cycles to stabilize after exit. |
| 21, 25 | LpBy / LnBy | Positive/negative ladder bypass - connect 0.1µF capacitors to improve internal reference stability and reduce noise coupling. |
| 22 | NC | No connection - must remain unconnected; not internally bonded or tested. |
| 23 | 1VREF | +1.0V unbuffered reference output - not intended for external loading; leave floating in normal operation. |
| 24, 27 | IN / IN | Differential analog inputs - IN (Pin 27) is primary input; IN (Pin 24) is complementary; tied to CM for single-ended use. |
| 26 | CM | Common-mode voltage output (+1.5V) - used to bias external driving circuitry or transformer center-tap in differential mode. |
Key Features
| Feature | Design Value |
|---|---|
| Digital error correction architecture | Guarantees no missing codes and ±0.7LSB DNL at 500kHz, enabling reliable imaging and video digitization without calibration. |
| Internal dual-reference ladder (+1.25V / +1.75V) | Provides stable, matched reference voltages for pipeline stages and generates precise +1.5V CM for input biasing without external components. |
| Wideband track-and-hold (350MHz) | Supports undersampling of IF signals up to 350MHz (small-signal), essential for direct-conversion radio architectures and spectrum analyzers. |
| Independent LVDD supply pin | Allows digital output voltage levels to be optimized separately from analog supply, simplifying interface to 3V FPGA or ASIC logic families. |
| 5-cycle deterministic data latency | Enables precise timing alignment in synchronous systems such as digital downconverters and real-time signal processors. |
Applications
| Portable Instrumentation | IF and Baseband Communications |
|---|---|
Use Scenario: Handheld spectrum analyzers and portable oscilloscopes requiring high-fidelity signal capture in battery-powered form factors. IC Role / Device Role / Timing Role: Primary ADC digitizing RF/IF downconverted signals with minimal power and board space. Use Value: 52mW power dissipation and SSOP-28 footprint enable compact, thermally manageable designs without sacrificing 49dB SNR at baseband frequencies. |
Use Scenario: Cable modem upstream/downstream channel receivers processing QAM-modulated signals in DOCSIS-compliant hardware. IC Role / Device Role / Timing Role: High-linearity ADC in analog front-end for digitizing 5–65MHz downstream or 5–42MHz upstream bands. Use Value: 53dBFS SFDR at 500kHz ensures clean spectral representation of multi-tone QAM carriers, reducing bit error rate in noisy HFC networks. |
| Cable Modems | Set-Top Boxes |
Use Scenario: Embedded DOCSIS 3.0/3.1 cable modems performing real-time analog signal conditioning before digital demodulation. IC Role / Device Role / Timing Role: ADC capturing analog upstream burst transmissions with fast overvoltage recovery (2ns) to handle transient ingress noise. Use Value: 2ns overvoltage recovery time prevents bit errors during impulse noise events common in shared coaxial plant environments. |
Use Scenario: Digital television receivers converting analog video/audio inputs (NTSC/PAL) for MPEG encoding and HDMI output. IC Role / Device Role / Timing Role: Video ADC supporting composite/S-video digitization with <2.3% differential gain and <1° differential phase error. Use Value: Specified NTSC/PAL accuracy ensures broadcast-quality color fidelity without external calibration or post-processing compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS830U | 8-bit, 60MSPS, no internal reference, SOIC-20 package | Higher speed but lower resolution and no integrated reference; requires external REF and layout for noise-sensitive analog routing. | Select when system prioritizes sampling rate >20MSPS and can accommodate external reference design complexity. |
| MAX1186EEE+ | 10-bit, 40MSPS, internal reference, QSOP-28 package, 3.3V-only supply | Higher sampling rate and same resolution, but only specified for +3.3V operation and lacks SSOP-28 pin compatibility. | Select when 40MSPS capability is required and board layout allows QSOP-28 footprint and 3.3V-only supply constraint. |
Compared with ADS900E, ADS830U trades resolution and integration for speed and smaller package, while MAX1186EEE+ offers higher speed and same resolution but requires different supply and packaging - neither is pin-compatible, making ADS900E preferred for legacy SSOP-28 designs needing 10-bit/20MSPS with internal reference.
Availability
ADS900E is available at Aetrix Electronics and suitable for portable instrumentation, IF/baseband communications, and cable modem applications requiring stable component supply across extended temperature ranges (–40°C to +85°C).
Supply support for ADS900E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-performance data converters.
The ADS900E belongs to TI's precision high-speed ADC product line, designed specifically for demanding communications, test equipment, and video digitization applications where resolution, linearity, and low-power operation are critical.
FAQ
What is the maximum sampling rate supported by the ADS900E?
The ADS900E is fully specified for operation at 20 million samples per second (20MSPS). This rate is validated across the full operating temperature range (–40°C to +85°C) and supply voltage range (+2.7V to +3.7V). At 20MSPS, the device maintains its published dynamic performance including 49dB SNR at 500kHz and 53dBFS SFDR, making it suitable for IF sampling in communications receivers and real-time test instrumentation where timing determinism is essential. The ADS900E does not support guaranteed operation above 20MSPS.
Does the ADS900E require external reference components?
No, the ADS900E does not require external reference components. It integrates a precision internal reference ladder that provides fixed +1.25V (REFB) and +1.75V (REFT) reference voltages, generating a stable +1.5V common-mode voltage (CM) at Pin 26. Pins 21 (LpBy) and 25 (LnBy) are provided for optional 0.1µF bypass capacitors to enhance reference stability, but no external resistors, op-amps, or voltage references are needed for basic operation. The +1.0V output at Pin 23 is unbuffered and intended to remain unconnected.
How does the power-down mode function on the ADS900E?
The ADS900E enters power-down mode when Pin 17 (Pwrdn) is driven high, reducing supply current by approximately 70% to ~10mW. During power-down, digital outputs enter high-impedance state and conversion accuracy is suspended. After Pwrdn is returned low, the first five clock cycles produce invalid data due to internal pipeline reset latency. An internal 50kΩ pull-down resistor ensures the device remains active by default if Pwrdn is left unconnected. Power-down recovery time is 18ns from Pwrdn high-to-low transition to valid output enable.
What is the purpose of the LVDD pin on the ADS900E?
The LVDD pin (Pin 2) supplies power exclusively to the digital output drivers of the ADS900E, allowing independent control of logic voltage levels. This enables direct interfacing with 3V FPGA or ASIC I/O banks without level shifters. When LVDD = +3V, output high voltage (VOH) is ≥+2.4V and output low voltage (VOL) is ≤+0.4V - meeting TTL/HCT and low-voltage CMOS thresholds. Driving LVDD to other voltages scales VOH/VOL proportionally, but TI specifies performance only at +3V. LVDD must be decoupled locally with a 0.1µF capacitor.
Can the ADS900E operate with a single-ended input configuration?
Yes, the ADS900E is explicitly designed for single-ended operation. In this mode, the complementary input (Pin 24) is tied to the common-mode voltage (Pin 26, +1.5V), converting the single-ended signal (applied to Pin 27) into a fully differential signal internally. This configuration provides 2× gain, improving SNR performance. The specified single-ended input range is +1.0V to +2.0V, centered at +1.5V. TI provides application circuits (e.g., Figure 3 and Figure 6 in SBAS058A) using op-amps like OPA680 to condition ground-referenced signals for this mode.
ADS900E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SpeedPlus™
- Package/Case:
- 28-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- 10
- Sampling Rate (Per Second):
- 20M
- Number of Inputs:
- 1
- Input Type:
- Differential, Single Ended
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 2.7V ~ 3.7V
- Voltage - Supply, Digital:
- 2.7V ~ 3.7V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 28-SSOP
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS900E FAQ
1.How can I place an order for ADS900E through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS900E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS900E reliable?
The price and inventory of ADS900E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS900E is usually 5 days.
3.What payment methods are accepted for ADS900E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS900E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS900E?
ADS900E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS900E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS900E?
For technical support, including ADS900E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS900E requirements.
6.How does Aetrix verify that ADS900E is sourced from the original manufacturer or authorized distributors?
All ADS900E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS900E meets industry standards.
7.What is the process for return or replacement of ADS900E?
All ADS900E units undergo pre-shipment inspection (PSI). If there is an issue with ADS900E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS900E part is unused and in its original packaging.
Return procedure for ADS900E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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