Texas Instruments ADS901E/1K

Overview

ADS901E/1K from Texas Instruments is a 10-bit, 20 MSPS pipelined analog-to-digital converter operating from a +3V single supply, featuring wideband track/hold (350 MHz small-signal bandwidth), digital error correction for no missing codes, and external reference inputs (REFB/REFT) to set 1V_p-p full-scale range. It targets high-fidelity imaging and video digitization where SNR ≥53 dB at 500 kHz and SFDR ≥50 dBFS are required.

For engineers reviewing the ADS901E/1K datasheet, ADS901E/1K pinout, ADS901E/1K application, or ADS901E/1K equivalent, this page delivers verified electrical specs (e.g., 5-cycle latency, ±0.8 LSB DLE, 3 ns aperture delay), SSOP-28 package mapping, real-world interface constraints (CMOS-compatible outputs, LVDD-supplied digital drivers), and two validated alternative ADCs with documented functional trade-offs.

Technical Context

The ADS901E/1K implements a 9-stage pipelined quantizer architecture with two-bit per stage resolution and redundant bits fed into a digital error correction circuit-guaranteeing no missing codes and ±0.8 LSB differential linearity at 500 kHz. Its fully differential track/hold accepts single-ended inputs and generates a held DC representation referenced to V_CM = (REFT + REFB)/2.

It uses straight offset binary coding, supports 3-state outputs via OE (pin 16), and enters low-power mode (<15 mW) when Pwrdn (pin 17) is asserted high. Digital outputs are isolated on dedicated LVDD (pin 2), enabling level-shifting compatibility with 3V logic while maintaining analog supply integrity.

Key Specifications

Pinout & Package

ADS901E/1K is housed in a 28-pin SSOP (Shrink Small Outline Package) with 0.65 mm pitch, JEDEC MO-153 compliant, MSL Level-2-260°C-1 year rating, and exposed pad not present. Pin 1 is marked by a beveled corner; pins 13/14/19/20 are analog ground; pins 1/18/28 are +VS analog supply; pin 2 is LVDD for digital output drivers.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 10-bit, 20 MSPS pipeline ADC applications.

Compared with MAX1180BCJ+ and AD9215BRUZ-20, the ADS901E/1K uniquely combines externally adjustable full-scale range, guaranteed no missing codes, and lowest power (48 mW) among 20 MSPS 10-bit pipeline ADCs - making it optimal for portable imaging and video where reference flexibility and thermal efficiency are design priorities.

Availability

ADS901E/1K is available at Aetrix Electronics and suitable for medical ultrasound imaging, digital camcorder video capture, and computer scanner analog front-ends requiring stable component supply, long-term lifecycle support, and RoHS-compliant SSOP packaging.

Supply support for ADS901E/1K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters, with over 50 years of innovation in precision signal chain solutions.

The ADS901E/1K belongs to TI's high-speed pipeline ADC product line, designed specifically for demanding imaging, video, and communications applications where low power, excellent linearity, and flexible reference architecture are essential.

FAQ

What is the absolute maximum input voltage range for the ADS901E/1K analog input pin?

The ADS901E/1K analog input (pin 27) has an absolute maximum rating of +VS + 0.3V. With +VS = +3V, this means the input must not exceed +3.3V. The specified full-scale range is 1V_p-p centered at +1.5V (i.e., +1V to +2V), and operation outside this range risks degraded linearity or saturation. Exceeding +3.3V may cause permanent damage per the Absolute Maximum Ratings table in SBAS054A.

Does the ADS901E/1K require separate analog and digital ground planes?

No - the ADS901E/1K does not have isolated analog and digital supply pins; all +VS pins (1, 18, 28) are internally connected to the same analog supply domain. TI explicitly recommends treating the device as analog-only and powering it solely from a clean analog supply. Digital noise coupling is mitigated by the dedicated LVDD (pin 2) for outputs and strict grounding of all GND pins (13, 14, 19, 20) to a single low-impedance analog ground plane.

How does the power-down mode affect data validity in the ADS901E/1K?

When Pwrdn (pin 17) is asserted high, the ADS901E/1K enters power-down mode and draws only 15 mW. During this state, digital outputs go to high-impedance, and conversion accuracy is lost. After returning Pwrdn to low, the first five output words following the next CLK edge are invalid due to pipeline reset latency - valid data resumes on the sixth sample. This behavior is documented in the Timing Diagram and Power-Down Mode section of SBAS054A.

Can the ADS901E/1K interface directly to 1.8V logic systems?

No - the ADS901E/1K digital outputs are CMOS-compatible but require LVDD ≥2.4V to guarantee VOH ≥2.4V and VOL ≤0.4V. Driving LVDD at 1.8V violates the specified logic thresholds and risks misreads by downstream 1.8V receivers. To interface with 1.8V logic, external level-shifting buffers or latches (with 1.8V-compatible inputs) must be used, as recommended in the Digital Outputs section of SBAS054A.

What is the purpose of the CM (pin 26) output on the ADS901E/1K?

The CM (Common-Mode) pin on the ADS901E/1K provides a buffered output of V_CM = (REFT + REFB)/2 - the mid-point voltage derived from the external reference ladder. It is intended to drive the common-mode bias of external driver amplifiers (e.g., OPA680 in Figure 3), ensuring matched DC offsets between the ADC input and its preceding signal conditioning stage. This minimizes common-mode rejection errors and improves overall system SNR.