Analog Devices Inc. ADSP-21060CW-133

Overview

ADSP-21060CW-133 from Analog Devices is a 32-bit floating-point SHARC® digital signal processor with 4 Mbit dual-ported on-chip SRAM, 40 MIPS instruction rate at 40 MHz, and IEEE 754-compliant 32-bit/40-bit floating-point computation units. It serves as the core computational engine in real-time audio processing, radar signal conditioning, and medical imaging systems requiring deterministic low-latency execution.

For engineers reviewing the ADSP-21060CW-133 datasheet, ADSP-21060CW-133 pinout, ADSP-21060CW-133 application, or ADSP-21060CW-133 equivalent, key selection criteria include sustained 80 MFLOPS performance, glueless multiprocessor support via six link ports, host interface compatibility with 16-/32-bit microprocessors, and thermal-enhanced MQFP_PQ4 packaging for industrial-grade reliability.

Technical Context

The ADSP-21060CW-133 implements the Super Harvard Architecture with four independent buses enabling simultaneous dual data fetch, instruction fetch, and nonintrusive I/O-achieving single-cycle instruction execution and parallel multiply-ALU operations. Its dual data address generators (DAG1/DAG2) support hardware bit-reverse and modulo addressing essential for FFT and filter implementations.

It integrates a dedicated I/O processor, 10-channel DMA controller supporting background transfers up to 240 MBps, and JTAG-compliant IEEE 1149.1 test access port for on-chip emulation. Memory mapping includes unified 4-gigaword external address space with programmable wait states and page-mode DRAM support.

Key Specifications

Pinout & Package

ADSP-21060CW-133 is housed in a 240-lead thermally enhanced MQFP_PQ4 package (28 mm × 28 mm, 0.5 mm pitch), RoHS compliant, with exposed thermal pad for industrial thermal management.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar floating-point DSP applications.

Compared with ADSP-21060C, ADSP-21060CW-133 offers superior thermal performance in industrial environments due to its thermally enhanced MQFP_PQ4 package, while ADSP-21062 trades half the SRAM for lower cost and power - making ADSP-21060CW-133 optimal for memory-intensive real-time signal processing where thermal stability is critical.

Availability

ADSP-21060CW-133 is available at Aetrix Electronics and suitable for audio signal processing, radar beamforming, and medical ultrasound imaging requiring stable component supply across extended product lifecycles.

Supply support for ADSP-21060CW-133 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The SHARC® processor family, including ADSP-21060CW-133, was engineered for computationally intensive real-time signal processing in communications, imaging, and industrial control systems demanding IEEE-compliant floating-point precision and deterministic timing.

FAQ

What is the maximum sustained floating-point performance of the ADSP-21060CW-133?

The ADSP-21060CW-133 delivers 80 MFLOPS sustained performance under real-world workloads such as 1024-point complex FFTs, validated per Analog Devices' benchmark data (Rev. H, p.4). This is achieved through parallel ALU/multiplier execution, dual-ported SRAM bandwidth, and zero-overhead loop control - not theoretical peak values. The ADSP-21060CW-133 maintains this throughput continuously during kernel execution without throttling.

Does the ADSP-21060CW-133 support direct connection to a 32-bit host microprocessor?

Yes, the ADSP-21060CW-133 includes a dedicated 32-bit host port with asynchronous HBR/HBG/REDY handshaking, enabling memory-mapped read/write access to its internal SRAM and IOP registers without external logic. The host can initiate DMA transfers and configure mailbox registers directly - confirmed in the "Host Processor Interface" section of the datasheet (Rev. H, p.5).

How many link ports does the ADSP-21060CW-133 have, and what is their aggregate bandwidth?

The ADSP-21060CW-133 features six independent 4-bit link ports, each capable of transferring 8 bits per core cycle at 40 MHz, yielding an aggregate bandwidth of 240 MBps. These ports support point-to-point interprocessor communication in multiprocessing systems and are fully programmable for transmit/receive direction - detailed in the "Link Ports" section (Rev. H, p.8).

What boot sources are supported by the ADSP-21060CW-133 at power-up?

The ADSP-21060CW-133 supports three boot modes selected via BMS, EBOOT, and LBOOT pins: 8-bit EPROM, host processor (16-/32-bit), or link port. Boot configuration is latched at reset and determines the initial instruction fetch path - documented in the "Program Booting" section (Rev. H, p.8) and Pin Descriptions table (p.10).

Is the ADSP-21060CW-133 pin-compatible with other members of the ADSP-2106x family?

The ADSP-21060CW-133 shares identical pinout and electrical characteristics with ADSP-21060 and ADSP-21060C in the 240-lead MQFP_PQ4 and CQFP packages respectively, as confirmed by the "240-Lead MQFP_PQ4/CQFP Pin Configuration" diagram (Rev. H, p.54). However, voltage variants (e.g., ADSP-21060L) require separate 3.3 V design considerations and are not drop-in replacements.