Analog Devices Inc. ADSP-21060CW-160

Overview

ADSP-21060CW-160 from Analog Devices is a 32-bit floating-point SHARC® digital signal processor with 4 Mbit dual-ported on-chip SRAM, 40 MIPS instruction rate at 40 MHz, IEEE 32-bit/40-bit floating-point computation units, and integrated host interface, DMA controller, six link ports, and two serial ports - deployed in real-time audio processing, radar beamforming, and medical imaging systems.

For engineers reviewing the ADSP-21060CW-160 datasheet, ADSP-21060CW-160 pinout, ADSP-21060CW-160 application, or ADSP-21060CW-160 equivalent, key selection criteria include on-chip memory size (4 Mbit), 5 V operation, MQFP_PQ4 package compatibility, and support for glueless multiprocessing via 240 MBps link port transfers.

Technical Context

The ADSP-21060CW-160 implements a Super Harvard Architecture with four independent buses enabling simultaneous dual data fetch, instruction fetch, and nonintrusive I/O. Its core integrates parallel ALU, multiplier, and shifter units executing single-cycle IEEE 32-bit floating-point operations and supporting zero-overhead looping.

It features dual data address generators with hardware circular buffering, an on-chip instruction cache for conflict-free three-bus operation, and distributed bus arbitration logic for scalable glueless multiprocessing across up to six devices. Memory-mapped I/O and unified 4-gigaword address space enable direct interprocessor access without external logic.

Key Specifications

Pinout & Package

ADSP-21060CW-160 is housed in a 240-lead thermally enhanced MQFP_PQ4 package with 0.5 mm lead pitch and exposed thermal pad. Pin functions are defined per Analog Devices Rev. H datasheet, including dedicated address/data multiplexed buses, link port signals (LxDAT3–0, LxCLK, LxACK), serial port lines (DR0/DT0/RCLK0/TCLK0), host interface control (HBR/HBG/REDY), and JTAG test access (TCK/TMS/TDI/TDO).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar floating-point DSP applications.

Compared with ADSP-21060CW-160, ADSP-21062W-160 trades half the on-chip SRAM for identical compute throughput in space-constrained systems, while ADSP-21060LCW-160 delivers equivalent performance at lower voltage but introduces interface compatibility considerations with 5 V peripherals.

Availability

ADSP-21060CW-160 is available at Aetrix Electronics and suitable for audio signal processing, radar beamforming, and medical imaging reconstruction requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized channels.

Supply support for ADSP-21060CW-160 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, headquartered in Norwood, MA, with design centers and manufacturing facilities worldwide.

The ADSP-21060CW-160 belongs to the SHARC® processor family - engineered for computationally intensive, real-time signal processing in communications, imaging, and industrial control where deterministic floating-point performance and on-chip integration are critical.

FAQ

What is the operating voltage specification for the ADSP-21060CW-160?

The ADSP-21060CW-160 operates at 5 V ± 5%, with separate 5 V supplies required for core (VDD), I/O (VDDIO), and analog (AVDD) domains. This 5 V requirement is confirmed in Table 1 and "Operating Conditions (5 V)" section of the Rev. H datasheet, and defines compatibility with legacy TTL/CMOS peripherals and memory devices without level translation.

Does the ADSP-21060CW-160 support JTAG debugging?

Yes, the ADSP-21060CW-160 includes a fully compliant IEEE 1149.1 JTAG Test Access Port (TAP) with TCK, TMS, TDI, TDO, and TRST pins. This enables boundary scan testing, in-circuit emulation, and real-time debug via Analog Devices EZ-ICE emulators - all documented in the "JTAG Test and Emulation" block diagram and "Pin Function Descriptions" sections of the datasheet.

How much on-chip memory does the ADSP-21060CW-160 integrate?

The ADSP-21060CW-160 integrates 4 Mbit (512 kwords × 8-bit) of dual-ported SRAM, organized as two 2 Mbit blocks. As specified in Table 1 and the "Dual-Ported On-Chip Memory" section, this allows independent single-cycle access by the core processor and DMA controller - essential for real-time streaming applications such as ultrasound data acquisition.

What package type is used for the ADSP-21060CW-160?

The ADSP-21060CW-160 uses a 240-lead thermally enhanced MQFP_PQ4 package with gull-wing leads and an exposed thermal pad. This package variant is explicitly listed in Table 1 and the "Outline Dimensions" section (Page 56) of the Rev. H datasheet, and is distinct from the PBGA and CQFP variants offered in the same SHARC family.

Can the ADSP-21060CW-160 operate in a multiprocessor configuration?

Yes, the ADSP-21060CW-160 supports glueless multiprocessing via its integrated multiprocessor interface, six link ports, and distributed bus arbitration logic. As detailed in Figure 3 and the "Multiprocessing" section, up to six ADSP-21060CW-160 devices can be interconnected with 240 MBps interprocessor transfer rates and broadcast write capability - eliminating need for external arbitration logic.