Analog Devices Inc. ADSP-21060KBZ-160

Overview

ADSP-21060KBZ-160 from Analog Devices is a 32-bit floating-point SHARC® digital signal processor with 4 Mbit dual-ported on-chip SRAM, 40 MIPS/120 MFLOPS peak performance, and 240-lead thermally enhanced MQFP_PQ4 package. It integrates instruction cache, six link ports, two serial ports, host interface, and DMA controller for real-time audio, radar, and medical imaging systems.

For engineers reviewing the ADSP-21060KBZ-160 datasheet, ADSP-21060KBZ-160 pinout, ADSP-21060KBZ-160 application, or ADSP-21060KBZ-160 equivalent, key selection criteria include on-chip memory size (4 Mbit), 5 V operation, 40 MHz instruction rate, dual-ported SRAM access concurrency, and glueless multiprocessing support via link/external bus.

Technical Context

The ADSP-21060KBZ-160 implements the Super Harvard Architecture with four independent buses enabling simultaneous instruction fetch, dual data fetch, and nonintrusive I/O. Its core includes parallel 32-bit IEEE floating-point multiplier, ALU, and shifter with single-cycle execution and zero-overhead looping.

It features dual data address generators with hardware circular buffer support, 48-bit instruction word for conditional parallel operations, and JTAG-compliant on-chip emulation. Memory subsystem comprises two 2 Mbit dual-ported SRAM blocks accessible independently by core and DMA/IOP at full speed.

Key Specifications

Pinout & Package

ADSP-21060KBZ-160 uses a 240-lead thermally enhanced MQFP_PQ4 package with 0.5 mm lead pitch and exposed thermal pad. Pinout follows standard ADSP-21060 family configuration per Analog Devices Rev. H datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar floating-point DSP applications.

Compared with ADSP-21060KBZ-160, ADSP-21060CZ-160 offers hermetic reliability at higher cost and weight, while ADSP-21062KBZ-160 reduces on-chip memory by 50% but maintains identical speed, voltage, package footprint, and peripheral set for cost-sensitive deployments.

Availability

ADSP-21060KBZ-160 is available at Aetrix Electronics and suitable for audio processing systems, radar signal processors, medical imaging subsystems, and industrial motor control applications requiring stable component supply and long-term industrial lifecycle support.

Supply support for ADSP-21060KBZ-160 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, headquartered in Norwood, MA, serving industrial, automotive, communications, and healthcare markets.

The ADSP-21060KBZ-160 belongs to the SHARC® processor family designed for computationally intensive, real-time floating-point signal processing in communications infrastructure, medical imaging, and test equipment.

FAQ

What is the operating voltage requirement for the ADSP-21060KBZ-160?

The ADSP-21060KBZ-160 operates at 5 V ± 0.25 V. It is not compatible with 3.3 V supply rails. This distinguishes it from the ADSP-21060L and ADSP-21060LC variants, which require 3.3 V. Power sequencing must ensure VDD reaches nominal level before CLKIN is applied, per Analog Devices Rev. H specifications.

Does the ADSP-21060KBZ-160 support JTAG-based debugging?

Yes, the ADSP-21060KBZ-160 includes full IEEE 1149.1 JTAG Test Access Port (TAP) support for boundary scan, in-circuit emulation, and real-time trace. Debugging requires an Analog Devices-compatible emulator (e.g., ICE-1000/2000) connected via the 14-pin JTAG header defined in the datasheet. The ADSP-21060KBZ-160's TAP enables halting, register inspection, and breakpoint setting without modifying target code.

How much on-chip memory does the ADSP-21060KBZ-160 provide, and how is it organized?

The ADSP-21060KBZ-160 provides 4 Mbit of on-chip SRAM, split into two dual-ported 2 Mbit blocks. Each block supports independent, single-cycle access by the core processor and DMA/IOP simultaneously. Memory can be configured as 128k × 32-bit data, 256k × 16-bit data, or 80k × 48-bit instructions - all accessible within the unified address space of the ADSP-21060KBZ-160.

Can the ADSP-21060KBZ-160 interface directly with a 32-bit host microprocessor?

Yes, the ADSP-21060KBZ-160 supports asynchronous host interface operation with both 16-bit and 32-bit microprocessors. Using HBR/HBG/REDY handshake signals and memory-mapped addressing, the host can read/write ADSP-21060KBZ-160 internal memory and registers at up to the DSP's full 40 MHz clock rate without additional glue logic.

What boot sources are supported by the ADSP-21060KBZ-160 at power-up?

The ADSP-21060KBZ-160 supports three boot modes selected by BMS, EBOOT, and LBOOT pins: 8-bit EPROM, host processor (16-/32-bit), or link port. Boot mode configuration is latched at reset release. No-boot mode is also available, directing execution to external memory. All boot methods load code into internal SRAM before execution begins on the ADSP-21060KBZ-160.