Analog Devices Inc. ADSP-21060LAB-160

Overview

ADSP-21060LAB-160 from Analog Devices is a 32-bit floating-point SHARC® digital signal processor with 4 Mbit dual-ported on-chip SRAM, 40 MIPS instruction rate at 40 MHz, IEEE 32-bit/40-bit floating-point computation units, and integrated host interface, DMA controller, six link ports, and two serial ports. It serves as the core computational engine in real-time audio processing, radar signal conditioning, and medical imaging systems.

For engineers reviewing the ADSP-21060LAB-160 datasheet, ADSP-21060LAB-160 pinout, ADSP-21060LAB-160 application, or ADSP-21060LAB-160 equivalent, key selection criteria include on-chip memory size (4 Mbit), 240-pin MQFP_PQ4 package compatibility, 5 V operation, and support for glueless multiprocessing via link and external ports.

Technical Context

The ADSP-21060LAB-160 implements the Super Harvard Architecture with four independent buses enabling simultaneous dual data fetch, instruction fetch, and nonintrusive I/O. Its core integrates parallel ALU, multiplier, and shifter units executing single-cycle 32-bit or 40-bit floating-point operations.

It features dual data address generators with hardware circular buffer support, zero-overhead looping, and an on-chip instruction cache that enables three-bus operation-fetching one instruction and two operands per cycle-critical for sustained FFT and FIR filter execution.

Key Specifications

Pinout & Package

ADSP-21060LAB-160 is housed in a 240-lead thermally enhanced MQFP_PQ4 package with 0.5 mm lead pitch, designed for high-density PCB layouts and efficient heat dissipation in convection-cooled systems.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar floating-point DSP applications.

Compared with ADSP-21060CAB-160, ADSP-21060LAB-160 offers superior thermal performance in standard industrial enclosures due to MQFP_PQ4's enhanced heatsinking; compared with ADSP-21062LAB-160, it delivers double on-chip memory bandwidth for large FFTs and coefficient tables without external memory access penalties.

Availability

ADSP-21060LAB-160 is available at Aetrix Electronics and suitable for audio signal processing, radar beamforming, and medical ultrasound imaging requiring stable component supply across long-lifecycle industrial programs.

Supply support for ADSP-21060LAB-160 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The SHARC® processor family-including ADSP-21060LAB-160-is engineered for computationally intensive, real-time signal processing in communications, imaging, and industrial control where deterministic floating-point performance and on-chip system integration are critical.

FAQ

What is the operating voltage requirement for ADSP-21060LAB-160?

ADSP-21060LAB-160 requires a nominal 5 V ± 5% supply voltage for core and I/O operation. This matches legacy industrial power architectures and eliminates level-shifting components when interfacing with 5 V DACs, ADCs, or FPGAs. The device draws up to 1.2 A under full 40 MHz load, necessitating adequate decoupling and thermal management per the Analog Devices thermal design guidelines.

Does ADSP-21060LAB-160 support JTAG-based in-circuit emulation?

Yes, ADSP-21060LAB-160 includes a fully compliant IEEE 1149.1 JTAG Test Access Port (TAP) for boundary-scan testing and real-time in-circuit emulation. When used with Analog Devices EZ-ICE emulators, it enables non-intrusive code download, breakpoint setting, register/memory inspection, and real-time trace-all without disrupting system timing. The JTAG interface remains active even during low-power modes.

How does the dual-ported SRAM in ADSP-21060LAB-160 improve real-time performance?

The 4 Mbit dual-ported SRAM in ADSP-21060LAB-160 consists of two independent 2 Mbit blocks, each accessible simultaneously by the core processor and DMA controller. This eliminates bus arbitration delays during streaming operations-for example, allowing the core to execute FFT butterfly stages while DMA loads new sample blocks into the alternate memory bank-achieving sustained 80 MFLOPS without external memory bottlenecks.

Can ADSP-21060LAB-160 be used in multiprocessor configurations without external arbitration logic?

Yes, ADSP-21060LAB-160 supports glueless multiprocessing via its integrated distributed bus arbitration logic and six dedicated link ports. Up to six ADSP-21060LAB-160 devices can be interconnected in a shared-memory topology with broadcast writes and vector interrupts, enabling scalable radar or audio array processing without FPGA or ASIC glue logic-reducing BOM cost and PCB complexity.

What boot options are available for ADSP-21060LAB-160 at power-up?

ADSP-21060LAB-160 supports three boot sources controlled by BMS, EBOOT, and LBOOT pins: 8-bit EPROM (via external address/data bus), host processor (16-/32-bit parallel interface), or link port (for daisy-chained configuration). Boot mode selection is latched at reset, enabling flexible system initialization-from standalone operation with local EPROM to host-controlled firmware updates over the link interface.