Analog Devices Inc. ADSP-21160NKB-100

Overview

ADSP-21160NKB-100 from Analog Devices is a 100 MHz, 32-bit SHARC® digital signal processor with dual computational units (PEX/PEY), 4M-bit on-chip dual-ported SRAM, and SIMD architecture enabling concurrent IEEE 32-/40-bit floating-point operations. It delivers 600 million math operations per second and targets high-throughput audio, medical imaging, and communications signal processing.

For engineers reviewing the ADSP-21160NKB-100 datasheet, ADSP-21160NKB-100 pinout, ADSP-21160NKB-100 application, or ADSP-21160NKB-100 equivalent, key selection criteria include core clock rate, SIMD-enabled computational throughput, glueless multiprocessing support via six link ports, and 400-ball PBGA package compatibility with legacy SHARC system designs.

Technical Context

The ADSP-21160NKB-100 implements a Super Harvard architecture with four independent buses-PM/DM address/data-enabling simultaneous instruction fetch, dual data read/write, and zero-overhead I/O. Its dual DAGs support hardware circular buffers and bit-reverse addressing essential for FFT and filter implementations.

It integrates an I/O processor with 14 zero-overhead DMA channels, six 8-bit link ports operating at 100 MB/s each, two TDM-capable serial ports (50 Mbps), and a 64-bit external parallel bus supporting glueless SBSRAM and multiprocessor interconnect. The on-chip PLL supports 2:1, 3:1, and 4:1 core-to-CLKIN ratios.

Key Specifications

Pinout & Package

ADSP-21160NKB-100 is housed in a 400-ball, 27 mm × 27 mm PBGA package with RoHS-compliant lead-free finish. Ball pitch is 1.27 mm. Thermal pad on underside requires proper PCB thermal relief per Analog Devices AN-711 guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital signal processor applications.

Compared with ADSP-21160NKB-100, ADSP-21161NKSZ-100 trades I/O scalability and memory capacity for compact packaging, while TMS320C6748ZWT shifts emphasis from deterministic signal processing to heterogeneous application processing-making ADSP-21160NKB-100 uniquely suited for high-channel-count, low-latency, glueless multiprocessor DSP systems.

Availability

ADSP-21160NKB-100 is available at Aetrix Electronics and suitable for professional audio equipment, medical ultrasound systems, military radar subsystems, and telecom baseband modems requiring stable component supply and long-term design continuity.

Supply support for ADSP-21160NKB-100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The SHARC® family-including ADSP-21160NKB-100-is engineered for computationally intensive, real-time signal processing in audio, imaging, and communications where deterministic latency, high floating-point throughput, and scalable multiprocessing are mandatory.

FAQ

What is the core instruction rate of the ADSP-21160NKB-100?

The ADSP-21160NKB-100 operates at a core instruction rate of 100 MHz (10 ns instruction cycle), delivering single-cycle execution for multiply, ALU, shifter, and register file operations. This rate is confirmed in the Rev. D datasheet's Operating Conditions section for the ADSP-21160N variant, which explicitly lists ADSP-21160NKB-100 as a 100 MHz ordering option before discontinuation.

Does the ADSP-21160NKB-100 support SIMD processing, and how is it enabled?

Yes, the ADSP-21160NKB-100 supports single-instruction, multiple-data (SIMD) processing using its two computational units (PEX and PEY). SIMD mode is enabled by setting the PEYEN bit in the MODE1 register. When active, both units execute identical instructions on independent data streams-doubling throughput for compatible algorithms like FIR filtering and FFT butterfly computation.

What package type and ball count does the ADSP-21160NKB-100 use?

The ADSP-21160NKB-100 uses a 400-ball plastic ball grid array (PBGA) package measuring 27 mm × 27 mm with 1.27 mm ball pitch. This package is RoHS-compliant and includes an exposed thermal pad on the underside, as documented in the "Package Information" section of the ADSP-21160M/ADSP-21160N Rev. D datasheet.

How much on-chip memory does the ADSP-21160NKB-100 integrate, and what is its architecture?

The ADSP-21160NKB-100 integrates 4 Mbits of on-chip SRAM organized as two independent 2 Mbit dual-ported blocks. Each block supports simultaneous single-cycle access by the core processor and I/O processor, enabling concurrent instruction fetch, data read/write, and DMA transfers without bus contention.

What are the primary I/O interfaces supported by the ADSP-21160NKB-100?

The ADSP-21160NKB-100 supports six 8-bit link ports (100 MB/s each), two synchronous serial ports (50 Mbps each with TDM and companding), a 64-bit external parallel bus, JTAG debug interface, and host processor interface compatible with 16-/32-bit microprocessors-all detailed in the "Memory and I/O Interface Features" section of the Rev. D datasheet.