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Home > Products > Integrated Circuits (ICs) > Embedded > DSP (Digital Signal Processors)

Analog Devices Inc. ADSP-21368BBPZ-2A

Name: ADSP-21368BBPZ-2A
Brand: Analog Devices Inc.
SKU: ADSP-21368BBPZ-2A
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADSP-21368BBPZ-2A

Manufacturer:: Analog Devices Inc.

Category:: DSP (Digital Signal Processors)

Package:: 256-LBGA Exposed Pad

Datasheet:: ADSP-21368BBPZ-2A.pdf

Description:: IC DSP 32BIT 333MHZ 256-BGA

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Product details

Overview

ADSP-21368BBPZ-2A from Analog Devices is a 32-bit/40-bit floating-point SHARC® DSP optimized for high-fidelity audio processing, featuring 400 MHz core instruction rate, 2 Mbits of on-chip SRAM, 6 Mbits of mask-programmable ROM, and integrated S/PDIF transceiver and 4-channel asynchronous sample rate converters (ASRC). It targets automotive infotainment head units requiring real-time FIR/IIR filtering, multi-channel audio mixing, and secure boot.

For engineers reviewing the ADSP-21368BBPZ-2A datasheet, ADSP-21368BBPZ-2A pinout, ADSP-21368BBPZ-2A application, or ADSP-21368BBPZ-2A equivalent, key selection criteria include SIMD computational throughput (2.4 GFLOPS), ROM-based security with 64-bit JTAG key enforcement, 256-ball BGA_ED package compatibility, and DAI-peripheral routing flexibility for custom audio I/O topologies.

Technical Context

The ADSP-21368BBPZ-2A implements a dual-processing-element SIMD core (PEx/PEy), each with ALU, multiplier, shifter, and 40-bit register file, enabling parallel execution of identical instructions on independent data streams. Its enhanced Harvard architecture supports simultaneous 64-bit PM and DM bus transfers plus instruction cache fetch in one cycle.

Peripherals are partitioned into core and I/O processor domains: the DAI includes four precision clock generators (PCG), eight serial ports (SPORTs), S/PDIF Tx/Rx, and four ASRC units; the DPI provides two UARTs, two SPIs, TWI, and three timers - all routed via flexible signal routing units (SRU) under software control.

Key Specifications

Parameter	Value and Actual Design Meaning
Core Frequency	400 MHz - enables 2.5 ns instruction cycle time and 2.4 GFLOPS peak performance for real-time audio algorithms.
On-Chip Memory	2 Mbits SRAM + 6 Mbits mask-ROM - supports full audio application code and data storage without external memory boot dependency.
S/PDIF Interface	Integrated transceiver - eliminates external codec interface ICs and simplifies AES3-compliant digital audio I/O design.
ASRC Channels	4 independent asynchronous sample rate converters - allows concurrent resampling of up to 4 stereo audio streams at different input/output rates (e.g., 44.1 kHz ↔ 48 kHz).
Serial Ports	8 SPORTs - deliver up to 32 I2S channels or 8 TDM streams (128 channels/frame), supporting multi-zone automotive audio distribution.
Security Model	ROM-based 64-bit JTAG key lock - prevents unauthorized firmware readout and enforces secure boot exclusively from internal ROM.
PWM Outputs	16 outputs (4 groups × 4) - configurable for center/edge-aligned waveforms with paired complementary signals for Class-D amplifier gate drive.

Pinout & Package

ADSP-21368BBPZ-2A is housed in a 256-ball BGA_ED package (17 mm × 17 mm, 1.0 mm pitch) with exposed thermal pad. Pin assignments follow the ADSP-21369-compatible 256-ball BGA_ED layout per Analog Devices documentation.

Pin/Terminal	Circuit Role	Design Meaning
B12, C12, D12, E12	S/PDIF_TX, S/PDIF_RX, S/PDIF_CLK, S/PDIF_FS	Dedicated differential-capable pins for biphase-mark encoded digital audio transmission/reception with frame sync and clock recovery.
A1–A16, B1–B16, C1–C16, D1–D16	DAI_P0–P31	Configurable digital I/O bank routed through DAI SRU - supports I2S, left-justified, or parallel IDP modes for flexible peripheral interconnect.
F1–F8, G1–G8	SPORT0–SPORT7	Eight independent synchronous serial port pairs - each with Tx/Rx, CLK, FS; supports TDM, I2S, and packed formats up to 50 Mbps.
H1–H4, J1–J4	PWM0–PWM15	16 PWM output terminals grouped as four sets of four - support center-aligned dual-update mode for low-harmonic Class-D amplifier control.
K1–K16	External Port Address/Data (AMI/SDRAM)	32-bit multiplexed address/data bus with bank select (MS0–MS3) - enables glueless interface to SDRAM (62M–64M words/bank) or asynchronous memory.
M1–M4, N1–N4	JTAG_TCK, TMS, TDI, TDO	IEEE 1149.1 boundary scan and emulation interface - requires valid 64-bit key for memory access when ROM security is enabled.

Key Features

Feature	Design Value
Dual SIMD Processing Elements (PEx/PEy)	Enables parallel execution of identical instructions on separate data streams - accelerates FIR, FFT, and matrix operations without code restructuring.
Digital Applications Interface (DAI) SRU	Software-configurable signal routing matrix - allows dynamic reassignment of S/PDIF, SPORT, PCG, and SRC signals to physical pins, reducing PCB layer count.
Four Precision Clock Generators (PCG)	Each generates independent audio clocks (e.g., 256×Fs, 512×Fs) with programmable jitter suppression - eliminates external clock synthesizers in multi-sample-rate systems.
Asynchronous Sample Rate Conversion (ASRC)	128 dB SNR conversion across 4 channels - maintains studio-grade audio fidelity during sample rate translation between disparate sources (e.g., Bluetooth A2DP ↔ USB Audio).
ROM-Based Security Enforcement	Blocks JTAG memory readout and external boot unless correct 64-bit key is scanned - ensures IP protection for proprietary audio algorithms in production units.

Applications

Automotive Infotainment Head Unit	Professional Digital Mixing Console
Use Scenario: Real-time multi-source audio blending (FM radio, Bluetooth, USB, HDMI ARC) with parametric EQ, loudness compensation, and speaker time-alignment. IC Role / Device Role / Timing Role: Primary audio processing engine executing 128-tap FIR filters, 32-band graphic EQ, and 8-channel ASRC with sub-microsecond latency. Use Value: On-chip 2 Mbits SRAM stores all filter coefficients and delay buffers; DAI SRU routes 8 SPORTs to ADC/DACs and S/PDIF to optical output without external logic.	Use Scenario: Low-latency channel strip processing (compression, gating, dynamics) across 32 input channels with independent sample rate handling (44.1/48/88.2/96 kHz). IC Role / Device Role / Timing Role: Core DSP running parallel SIMD algorithms on 32-channel interleaved data; ASRC units normalize inputs to internal 96 kHz domain. Use Value: 4 ASRC channels handle simultaneous resampling of 8 stereo inputs; 16 PWM outputs drive LED metering and relay control with precise timing alignment.
High-End Home Theater AV Receiver	Medical Ultrasound Beamformer
Use Scenario: Dolby Atmos and DTS:X object-based audio decoding with real-time spatial rendering to 11.2 speaker zones and subwoofer management. IC Role / Device Role / Timing Role: Secondary SHARC processor offloading immersive audio rendering from main SoC; synchronizes via DAI PCG clocks to master audio domain. Use Value: 6 Mbits ROM stores licensed decoder firmware; S/PDIF transceiver handles HDMI eARC return channel audio with zero external components.	Use Scenario: Digital beamforming of 128-channel ultrasound echo data with dynamic focusing, harmonic imaging, and Doppler processing. IC Role / Device Role / Timing Role: Real-time FIR filtering and complex envelope detection on 128-channel RF data streams using SIMD-optimized kernels. Use Value: Dual 64-bit PM/DM buses sustain 2×64-bit data transfers per cycle - meets >1.2 GB/s memory bandwidth requirement for 128-channel 40-MHz sampling.

Automotive Infotainment Head Unit

Professional Digital Mixing Console

Use Scenario: Real-time multi-source audio blending (FM radio, Bluetooth, USB, HDMI ARC) with parametric EQ, loudness compensation, and speaker time-alignment.

IC Role / Device Role / Timing Role: Primary audio processing engine executing 128-tap FIR filters, 32-band graphic EQ, and 8-channel ASRC with sub-microsecond latency.

Use Value: On-chip 2 Mbits SRAM stores all filter coefficients and delay buffers; DAI SRU routes 8 SPORTs to ADC/DACs and S/PDIF to optical output without external logic.

Use Scenario: Low-latency channel strip processing (compression, gating, dynamics) across 32 input channels with independent sample rate handling (44.1/48/88.2/96 kHz).

IC Role / Device Role / Timing Role: Core DSP running parallel SIMD algorithms on 32-channel interleaved data; ASRC units normalize inputs to internal 96 kHz domain.

Use Value: 4 ASRC channels handle simultaneous resampling of 8 stereo inputs; 16 PWM outputs drive LED metering and relay control with precise timing alignment.

High-End Home Theater AV Receiver

Medical Ultrasound Beamformer

Use Scenario: Dolby Atmos and DTS:X object-based audio decoding with real-time spatial rendering to 11.2 speaker zones and subwoofer management.

IC Role / Device Role / Timing Role: Secondary SHARC processor offloading immersive audio rendering from main SoC; synchronizes via DAI PCG clocks to master audio domain.

Use Value: 6 Mbits ROM stores licensed decoder firmware; S/PDIF transceiver handles HDMI eARC return channel audio with zero external components.

Use Scenario: Digital beamforming of 128-channel ultrasound echo data with dynamic focusing, harmonic imaging, and Doppler processing.

IC Role / Device Role / Timing Role: Real-time FIR filtering and complex envelope detection on 128-channel RF data streams using SIMD-optimized kernels.

Use Value: Dual 64-bit PM/DM buses sustain 2×64-bit data transfers per cycle - meets >1.2 GB/s memory bandwidth requirement for 128-channel 40-MHz sampling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-performance audio DSP applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADSP-21369BBCZ-4	Same SHARC family, 400 MHz, but in 256-ball BGA_ED package with extended temperature range (−40°C to +105°C) and higher SDRAM bandwidth.	Targeted at under-hood automotive modules requiring extended thermal operation and faster external memory access.	Select ADSP-21369BBCZ-4 when operating ambient exceeds 85°C or SDRAM throughput >664 MB/s is required.
ADSP-21479BSWZ-4	Newer SHARC+ core, 450 MHz, 512 kB L1 SRAM, no mask ROM, supports DDR2/3 via EMIF instead of SDRAM controller.	Designed for software-defined radio and radar where field-upgradable firmware and larger external memory are prioritized over ROM-based security.	Choose ADSP-21479BSWZ-4 for applications needing post-deployment firmware updates or DDR3 interfacing, not ROM-locked audio systems.

Compared with ADSP-21369BBCZ-4, ADSP-21368BBPZ-2A offers identical core performance and DAI peripherals but lacks extended temperature rating and has lower SDRAM bandwidth; versus ADSP-21479BSWZ-4, it trades modern memory interface and upgradeability for hardware-enforced IP protection and mature audio-optimized peripheral integration.

Availability

ADSP-21368BBPZ-2A is available at Aetrix Electronics and suitable for automotive infotainment, professional audio equipment, and medical ultrasound systems requiring stable component supply, long-term lifecycle assurance, and qualified industrial-grade packaging.

Supply support for ADSP-21368BBPZ-2A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, industrial automation, and communications infrastructure.

The SHARC processor product line was designed specifically for computationally intensive, low-latency audio and sensor signal processing applications - emphasizing deterministic real-time performance, on-chip memory bandwidth, and dedicated audio peripherals like ASRC and S/PDIF.

FAQ

What is the maximum sample rate supported by the ASRC units in ADSP-21368BBPZ-2A?

The ADSP-21368BBPZ-2A's four asynchronous sample rate converters support input and output sample rates from 8 kHz to 192 kHz, with 128 dB SNR performance across the full range. Each ASRC operates independently and can be configured for different source/target rates simultaneously - for example, converting 44.1 kHz Bluetooth audio and 48 kHz USB audio to a common 96 kHz internal processing domain within ADSP-21368BBPZ-2A.

Does ADSP-21368BBPZ-2A support JTAG debugging after ROM security is enabled?

Yes, ADSP-21368BBPZ-2A supports JTAG debugging with ROM security enabled, but only after successful scanning of the customer-specific 64-bit key via TDI/TDO. Without the correct key, JTAG access to internal memory and registers is blocked; with the key, full breakpoint-based software debug, memory inspection, and real-time trace remain available in ADSP-21368BBPZ-2A.

Can the 8 serial ports (SPORTs) in ADSP-21368BBPZ-2A operate at different clock domains simultaneously?

Yes, ADSP-21368BBPZ-2A's eight serial ports can operate in independent clock domains using dedicated precision clock generators (PCG0–PCG3). Each SPORT pair may be assigned to a unique PCG output, allowing concurrent operation at distinct sample rates - for instance, SPORT0–1 at 44.1 kHz for CD audio, SPORT2–3 at 48 kHz for digital TV, and SPORT4–7 at 96 kHz for high-res streaming - all synchronized internally within ADSP-21368BBPZ-2A.

What is the function of the DAI Signal Routing Unit (SRU) in ADSP-21368BBPZ-2A?

The DAI Signal Routing Unit (SRU) in ADSP-21368BBPZ-2A is a programmable interconnect matrix that dynamically routes signals between internal peripherals (S/PDIF, SPORTs, PCGs, ASRC) and physical DAI pins (DAI_P0–P31). This eliminates fixed hardware signal paths, enabling one ADSP-21368BBPZ-2A design to support multiple board variants - such as routing S/PDIF to optical output on one revision and to coaxial RCA on another - via firmware configuration alone.

Is ADSP-21368BBPZ-2A pin-compatible with ADSP-21369 devices?

Yes, ADSP-21368BBPZ-2A is pin-compatible with ADSP-21369 devices in the same 256-ball BGA_ED package, sharing identical pin functions, power sequencing, and thermal pad layout. However, ADSP-21368BBPZ-2A is a discontinued variant with identical core architecture and peripheral set but lacks the ADSP-21369's minor errata fixes and updated qualification data - confirmed in Analog Devices' Rev. H datasheet which explicitly lists ADSP-21368 as obsolete while retaining full pinout and functional equivalence for ADSP-21368BBPZ-2A.

ADSP-21368BBPZ-2A Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: SHARC®

Package/Case:: 256-LBGA Exposed Pad

Packaging:: Tray

Product Status:: Obsolete

Type:: Floating Point

Interface:: DAI, DPI

Clock Rate:: 333MHz

Non-Volatile Memory:: ROM (768kB)

On-Chip RAM:: 256kB

Voltage - I/O:: 3.30V

Voltage - Core:: 1.20V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 256-BGA-ED (27x27)

ADSP-21368BBPZ-2A FAQ

1.How can I place an order for ADSP-21368BBPZ-2A through Aetrix?

Please submit a Request for Quotation (RFQ) for ADSP-21368BBPZ-2A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADSP-21368BBPZ-2A reliable?

The price and inventory of ADSP-21368BBPZ-2A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-21368BBPZ-2A is usually 5 days.

3.What payment methods are accepted for ADSP-21368BBPZ-2A?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-21368BBPZ-2A transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADSP-21368BBPZ-2A?

ADSP-21368BBPZ-2A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADSP-21368BBPZ-2A order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADSP-21368BBPZ-2A?

For technical support, including ADSP-21368BBPZ-2A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-21368BBPZ-2A requirements.

6.How does Aetrix verify that ADSP-21368BBPZ-2A is sourced from the original manufacturer or authorized distributors?

All ADSP-21368BBPZ-2A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-21368BBPZ-2A meets industry standards.

7.What is the process for return or replacement of ADSP-21368BBPZ-2A?

All ADSP-21368BBPZ-2A units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-21368BBPZ-2A, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADSP-21368BBPZ-2A part is unused and in its original packaging.

Return procedure for ADSP-21368BBPZ-2A:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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