Analog Devices Inc. ADSP-21368KBPZ-3A
- Part No.:
- ADSP-21368KBPZ-3A
- Manufacturer:
- Analog Devices Inc.
- Category:
- DSP (Digital Signal Processors)
- Package:
- 256-LBGA Exposed Pad
- Datasheet:
-
ADSP-21368KBPZ-3A.pdf
- Description:
- IC DSP 32BIT 400MHZ 256BGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADSP-21368KBPZ-3A from Analog Devices is a 32-bit/40-bit floating-point SHARC® DSP optimized for high-fidelity audio processing, featuring 400 MHz core instruction rate, 2 Mbits of on-chip SRAM, 6 Mbits of mask-programmable ROM, and dedicated audiocentric peripherals including S/PDIF transceiver, 4-channel asynchronous sample rate converter (ASRC), and 16 PWM outputs. It targets automotive infotainment head units requiring real-time FIR/IIR filtering, multi-channel mixing, and secure boot.
For engineers reviewing the ADSP-21368KBPZ-3A datasheet, ADSP-21368KBPZ-3A pinout, ADSP-21368KBPZ-3A application, or ADSP-21368KBPZ-3A equivalent, key selection criteria include SIMD computational throughput (2.4 GFLOPS), ROM-based security with 64-bit JTAG key enforcement, dual-clock-domain architecture (core + I/O processor), and support for 32-bit SDRAM/AMI external memory interfaces.
Technical Context
The ADSP-21368KBPZ-3A implements a dual-processing-element (PEx/PEy) SIMD core with independent ALU, multiplier, shifter, and 40-bit register files per element, enabling parallel execution of identical instructions on distinct data streams. Its enhanced Harvard architecture supports simultaneous 64-bit PM and DM bus transfers plus instruction cache fetch in one cycle.
It integrates two clock domains: a 400 MHz core domain hosting computation and on-chip memory, and a peripheral domain managing DAI (digital applications interface), DPI (digital peripheral interface), S/PDIF, ASRC, and PWM modules via 32-bit IOD0/IOD1 buses. The DAI includes four precision clock generators (PCG), eight serial ports (SPORTs), and flexible signal routing (SRU) for dynamic interconnection of audio peripherals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Frequency | 400 MHz - enables 2.5 ns instruction cycle time and 2.4 GFLOPS peak performance for real-time audio algorithms. |
| On-Chip Memory | 2 Mbits SRAM + 6 Mbits mask-ROM - provides zero-wait-state storage for code/data; supports 16-/32-/48-/64-bit word access and 16-bit FP format doubling effective capacity. |
| S/PDIF Interface | Integrated transceiver - handles biphase-encoded digital audio I/O without external PHY; accepts left-justified, I2S, or right-justified formats at 16–24 bit word widths. |
| ASRC Channels | 4 independent asynchronous sample rate converters - enable seamless mixing of audio streams at differing sample rates (e.g., 44.1 kHz + 48 kHz) with 128 dB SNR performance. |
| PWM Outputs | 16 outputs grouped into four sets of four - configurable as center-aligned or edge-aligned waveforms; supports paired complementary outputs for motor/audio Class-D amplifier control. |
| Serial Ports | 8 SPORTs - deliver up to 32 transmit/receive channels or 128-channel TDM frames at ≤50 Mbps; support I2S, left-justified, packed I2S, and μ-law/A-law companding per channel. |
| External Memory Interface | 32-bit AMI + SDRAM controller - supports glueless connection to SRAM/Flash (14M–16M words/bank) and industry-standard SDRAM (62M–64M words/bank) with programmable timing. |
Pinout & Package
ADSP-21368KBPZ-3A is packaged in a 256-ball BGA_ED (ball pitch: 1.0 mm, body size: 17 mm × 17 mm) with thermal pad exposed on underside for enhanced heat dissipation in high-power audio processing applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DAI_P0–P23 | Digital Applications Interface I/O | Configurable multiplexed pins routed via SRU to S/PDIF, SPORTs, PCG, IDP, or ASRC - enables flexible hardware interconnect without PCB redesign. |
| SPORT0–7_TX/RX | Synchronous Serial Port Data | Dedicated high-speed serial lanes supporting 50 Mbps; each pair has independent DMA channel for zero-CPU-overhead audio streaming. |
| SCLK, SCLK2 | Core & Peripheral Clock Inputs | Accept external clocks (up to 400 MHz core, lower for peripheral domain); internal PLL generates precise frequencies for PCG, ASRC, and S/PDIF timing. |
| FLAG0–FLAG7 | General-Purpose I/O / Interrupt Flags | Programmable as GPIO or hardware interrupt sources; FLAG3 doubles as core timer expiration output for deterministic real-time scheduling. |
| ADDR[0:23], DATA[0:31] | External Memory Bus | 32-bit multiplexed address/data bus for AMI/SDRAM; supports burst transfers and bank arbitration for multi-device systems. |
| TCK, TMS, TDI, TDO | JTAG Test Access Port | IEEE 1149.1-compliant interface for emulation, boundary scan, and secure debug - requires valid 64-bit key to access memory when ROM security is enabled. |
Key Features
| Feature | Design Value |
|---|---|
| ROM-Based Security | Enforces exclusive boot from internal mask-ROM and disables JTAG memory access unless correct 64-bit key is scanned - prevents firmware extraction in production automotive ECUs. |
| Dual-Clock Domain Architecture | Separates 400 MHz compute-intensive core operations from lower-frequency peripheral management - eliminates I/O bottlenecks during sustained FFT or FIR processing. |
| Digital Applications Interface (DAI) | Software-configurable SRU matrix interconnects 8 SPORTs, S/PDIF, 4 PCGs, 4 ASRCs, and IDP - enables custom audio routing (e.g., S/PDIF → ASRC → SPORT → DAC) without external logic. |
| Asynchronous Sample Rate Conversion | Four independent ASRC blocks achieve 128 dB SNR and support real-time resampling between arbitrary sample rates (e.g., 44.1 kHz ↔ 48 kHz) for legacy source integration. |
| Enhanced Harvard Memory System | Two 64-bit core buses (PM/DM) + dual 32-bit I/O buses (IOD0/IOD1) allow concurrent 4-data-word + instruction fetch - sustains full 2.4 GFLOPS in SIMD mode without memory stalls. |
Applications
| Automotive Infotainment Head Unit | Digital Audio Workstation (DAW) Hardware |
|---|---|
Use Scenario: Real-time multi-zone audio processing with Bluetooth A2DP, USB audio, and analog radio inputs feeding a 12+ channel amplifier. IC Role / Device Role / Timing Role: Primary audio DSP executing FIR-based room correction, dynamic range compression, and 3D spatialization in <2 ms latency. Use Value: On-chip 2 Mbits SRAM stores filter coefficients and delay lines; 4 ASRCs synchronize mixed input sources; S/PDIF handles optical digital output to external DACs. |
Use Scenario: Low-latency plugin processing engine for professional recording interfaces handling 64+ channels at 96 kHz. IC Role / Device Role / Timing Role: Dedicated coprocessor offloading CPU-intensive convolution reverb, parametric EQ, and harmonic excitation from host system. Use Value: 2.4 GFLOPS SIMD performance executes 1024-pt complex FFT in 23.2 µs; 8 SPORTs route I/O across multiple ADC/DAC chips; ROM security protects proprietary algorithm IP. |
| High-End Home Theater Receiver | Pro Audio Digital Mixer |
Use Scenario: 11.2-channel surround sound decoding (Dolby Atmos, DTS:X) with object-based audio rendering and speaker calibration. IC Role / Device Role / Timing Role: Core audio processor managing ASRC-resampled streams, bass management, and real-time loudness normalization. Use Value: 6 Mbits ROM stores licensed codec libraries; 16 PWM outputs drive LED status indicators and relay control; DAI SRU routes HDMI ARC audio to internal processing path. |
Use Scenario: 32-in/32-out live mixing console with per-channel dynamics, EQ, and effects running at ≤1 ms round-trip latency. IC Role / Device Role / Timing Role: Main DSP engine performing channel strip processing, matrix routing, and monitor section control with deterministic timing. Use Value: Dual 64-bit memory buses sustain simultaneous 32-channel I/O buffering; 4 PCGs generate independent master clocks for different sample rate zones; JTAG key ensures firmware integrity during field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance audio DSP applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADSP-21369KBPZ-3A | Same package and pinout; adds 1 MB additional SRAM (3 Mbits total) and enhanced SDRAM controller timing flexibility. | Better suited for memory-intensive applications like large FIR filter banks or multi-layer neural network inference. | Select when >2 Mbits on-chip RAM is required and board layout accommodates identical 256-BGA footprint. |
| ADSP-21364KBPZ-3A | Lower 333 MHz core frequency; retains same 2 Mbits SRAM/6 Mbits ROM but omits S/PDIF and reduces ASRC count to 2 channels. | Targeted at cost-sensitive audio systems where S/PDIF I/O and advanced resampling are not required. | Choose for budget-constrained designs needing SHARC compatibility but without premium audio interface features. |
Compared with ADSP-21368KBPZ-3A, ADSP-21369KBPZ-3A delivers higher memory bandwidth and extended SDRAM timing control for larger external memory systems, while ADSP-21364KBPZ-3A sacrifices S/PDIF and ASRC capability to reduce cost and power - making the ADSP-21368KBPZ-3A the optimal balance of audio interface richness, computational throughput, and on-chip memory for mid-to-high-tier audio platforms.
Availability
ADSP-21368KBPZ-3A is available at Aetrix Electronics and suitable for automotive infotainment, professional audio hardware, and high-end home theater receivers requiring stable component supply, long lifecycle support, and guaranteed traceability.
Supply support for ADSP-21368KBPZ-3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, headquartered in Norwood, MA, with design centers worldwide and a 50+ year heritage in precision signal processing.
The SHARC® processor family was engineered specifically for computationally intensive, low-latency audio and industrial signal processing - emphasizing SIMD floating-point throughput, flexible I/O routing, and on-chip memory bandwidth over general-purpose CPU features.
FAQ
What is the maximum operating frequency of the ADSP-21368KBPZ-3A core?
The ADSP-21368KBPZ-3A operates at a maximum core frequency of 400 MHz, delivering a 2.5 ns instruction cycle time and 2.4 GFLOPS peak computational performance. This frequency is achieved using an internal PLL locked to an external reference clock, and it is fully supported across the specified industrial temperature range (−40°C to +85°C) with appropriate thermal management.
Does the ADSP-21368KBPZ-3A support secure boot and firmware protection?
Yes, the ADSP-21368KBPZ-3A implements ROM-based security that enforces boot exclusively from internal mask-programmable ROM and disables JTAG memory access unless a unique 64-bit key is scanned via the test access port. This prevents unauthorized firmware readout and ensures intellectual property protection in production audio systems.
How many serial audio interfaces does the ADSP-21368KBPZ-3A provide, and what protocols are supported?
The ADSP-21368KBPZ-3A integrates eight synchronous serial ports (SPORTs) supporting I2S, left-justified, right-justified, packed I2S, and μ-law/A-law companding protocols at word lengths from 3 to 32 bits. Each SPORT supports up to four channels, enabling configurations such as 32-channel I2S I/O or 128-channel TDM frames at ≤50 Mbps aggregate data rate.
Can the ADSP-21368KBPZ-3A perform sample rate conversion between different audio sources?
Yes, the ADSP-21368KBPZ-3A includes four independent asynchronous sample rate converters (ASRCs) capable of real-time resampling between arbitrary sample rates (e.g., 44.1 kHz ↔ 48 kHz) with 128 dB SNR performance. These ASRCs operate within the DAI and can be software-routed to accept input from SPORTs, S/PDIF, or IDP and feed output to any compatible peripheral.
What external memory interfaces are available on the ADSP-21368KBPZ-3A?
The ADSP-21368KBPZ-3A provides a 32-bit external port with dual controllers: an Asynchronous Memory Interface (AMI) supporting SRAM, Flash, and EPROM across four banks (14M–16M words/bank), and an SDRAM controller supporting industry-standard SDRAM devices up to 64M words per bank. Both interfaces operate gluelessly with programmable timing parameters.
ADSP-21368KBPZ-3A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- SHARC®
- Package/Case:
- 256-LBGA Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- Floating Point
- Interface:
- DAI, DPI
- Clock Rate:
- 400MHz
- Non-Volatile Memory:
- ROM (768kB)
- On-Chip RAM:
- 256kB
- Voltage - I/O:
- 3.30V
- Voltage - Core:
- 1.30V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 256-BGA-ED (27x27)
ADSP-21368KBPZ-3A FAQ
1.How can I place an order for ADSP-21368KBPZ-3A through Aetrix?
Please submit a Request for Quotation (RFQ) for ADSP-21368KBPZ-3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADSP-21368KBPZ-3A reliable?
The price and inventory of ADSP-21368KBPZ-3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-21368KBPZ-3A is usually 5 days.
3.What payment methods are accepted for ADSP-21368KBPZ-3A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-21368KBPZ-3A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADSP-21368KBPZ-3A?
ADSP-21368KBPZ-3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADSP-21368KBPZ-3A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADSP-21368KBPZ-3A?
For technical support, including ADSP-21368KBPZ-3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-21368KBPZ-3A requirements.
6.How does Aetrix verify that ADSP-21368KBPZ-3A is sourced from the original manufacturer or authorized distributors?
All ADSP-21368KBPZ-3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-21368KBPZ-3A meets industry standards.
7.What is the process for return or replacement of ADSP-21368KBPZ-3A?
All ADSP-21368KBPZ-3A units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-21368KBPZ-3A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADSP-21368KBPZ-3A part is unused and in its original packaging.
Return procedure for ADSP-21368KBPZ-3A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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