Analog Devices Inc. ADSP-21573KBCZ-5

Overview

ADSP-21573KBCZ-5 from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor, delivering 500 MHz per SHARC+ core and 500 MHz Arm Cortex-A5 operation. It features 3 Mb L1 SRAM per SHARC+ core (with parity), 256 kB L2 cache (parity), and supports 32-/40-/64-bit floating-point arithmetic. Designed for automotive audio processing, it integrates dual CAN 2.0 controllers, S/PDIF Rx/Tx, and AEC-Q100 qualification.

For engineers reviewing the ADSP-21573KBCZ-5 datasheet, ADSP-21573KBCZ-5 pinout, ADSP-21573KBCZ-5 application, or ADSP-21573KBCZ-5 equivalent, key selection criteria include dual SHARC+ core timing determinism, Arm Cortex-A5 Linux-capable subsystem integration, 400-ball CSP_BGA package constraints, and automotive-grade thermal/EMC robustness in safety-critical signal chains.

Technical Context

The ADSP-21573KBCZ-5 implements a heterogeneous dual-domain architecture: two SHARC+ cores operate at full 500 MHz with independent L1 SRAM banks (384 kB each) and SIMD computational units supporting IEEE 32/40/64-bit FP and 32-bit fixed-point operations; the Arm Cortex-A5 core runs at 500 MHz with 32 kB I-cache, 32 kB D-cache, and 256 kB L2 cache, all with parity protection. Both domains share a coherent system fabric with crossbar interconnect and DMA subsystem.

It integrates dedicated hardware acceleration including FIR/IIR offload engines, cryptographic accelerators, Arm TrustZone security, and ASRCs for sample-rate conversion. Peripherals include dual CAN 2.0 controllers, three UARTs, two SPI + quad-SPI, three I²C, USB 2.0 HS, EMAC, SDIO/eMMC, and an 8-channel 12-bit HADC - all mapped to a 400-ball CSP_BGA footprint with automotive temperature range support (-40°C to +125°C).

Key Specifications

Pinout & Package

ADSP-21573KBCZ-5 uses a 400-ball CSP_BGA package (17 mm × 17 mm, 0.65 mm pitch), RoHS-compliant, with ball pitch and mechanical dimensions defined in Analog Devices' ADSP-SC57x/2157x Outline Dimensions (Rev. C, p.138). Thermal pad exposed on underside for enhanced heat transfer.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP+Arm applications.

Compared with ADSP-SC573KBCZ-5, the ADSP-21573KBCZ-5 adds mandatory AEC-Q100 Grade 1 compliance and automotive-specific fault management; compared with ADSP-21573WBCZ-5, it offers cost-optimized qualification for cabin-integrated systems without under-hood thermal stress.

Availability

ADSP-21573KBCZ-5 is available at Aetrix Electronics and suitable for automotive infotainment, professional audio equipment, and industrial acoustic monitoring requiring stable component supply across extended product lifecycles.

Supply support for ADSP-21573KBCZ-5 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision, power, and connectivity applications.

The ADSP-21573KBCZ-5 belongs to the SHARC+ dual-core DSP family designed specifically for automotive and professional audio systems demanding deterministic real-time processing, functional safety, and secure software execution in a single chip.

FAQ

What is the maximum operating frequency of each SHARC+ core in the ADSP-21573KBCZ-5?

The ADSP-21573KBCZ-5 operates each SHARC+ core at up to 500 MHz, as confirmed in Table 2 of the Rev. C datasheet. This frequency is sustained across the full automotive temperature range (−40°C to +125°C) with appropriate voltage regulation and thermal management. The ADSP-21573KBCZ-5 does not support dynamic frequency scaling - the core clock is fixed at 500 MHz in production configuration.

Does the ADSP-21573KBCZ-5 support DDR3 memory interfacing?

Yes, the ADSP-21573KBCZ-5 includes a 16-bit DDR3/DDR2/LPDDR1 controller, as specified in Table 2 and Section "MEMORY" of the datasheet. It supports DDR3L (1.35 V) and standard DDR3 (1.5 V) devices, with configurable timing parameters for reliable operation up to 533 MHz data rate. This interface is accessible only on the 400-ball CSP_BGA package variant.

How many CAN 2.0 interfaces does the ADSP-21573KBCZ-5 integrate?

The ADSP-21573KBCZ-5 integrates two independent CAN 2.0B controllers, as documented in the "PERIPHERALS" block diagram (p.2), Table 1 ("Common Product Features"), and Table 2. Each controller supports bit rates up to 1 Mbps and includes dedicated message RAM, filtering, and loopback test modes - no external CAN transceivers are included on-die.

Is the ADSP-21573KBCZ-5 pin-compatible with other members of the ADSP-2157x family?

Yes, the ADSP-21573KBCZ-5 shares identical 400-ball CSP_BGA pinout with ADSP-21573WBCZ-5 and ADSP-SC573KBCZ-5, as verified in the "400-Ball CSP_BGA Signal Descriptions" (p.28) and "400-Ball BGA Ball Assignments" (p.127) sections. All three variants use the same mechanical outline, ball map, and electrical signaling - only factory-programmed configuration bits and qualification level differ.

What boot sources are supported by the ADSP-21573KBCZ-5?

The ADSP-21573KBCZ-5 supports boot from SPI flash, parallel NOR flash, SDIO/eMMC, USB 2.0 recovery mode, and internal L2 ROM - selected via BOOT_CFG[3:0] strap pins at power-up. Boot mode configuration is detailed in the "ADSP-SC57x/ADSP-2157x Designer Quick Reference" (p.45) and "System Design" section. No external boot ROM is required due to integrated 0.25 MB L2 boot ROM per core domain.

Does the ADSP-21573KBCZ-5 include hardware cryptographic acceleration?

Yes, the ADSP-21573KBCZ-5 includes dedicated cryptographic hardware accelerators supporting AES-128/256, SHA-256, RSA-2048, and ECC-256, as stated in the "ADDITIONAL FEATURES" section and "Security Features" chapter (p.13). These accelerators operate independently of the SHARC+ and Arm cores, enabling secure boot, firmware encryption, and runtime key management without CPU overhead.