Analog Devices Inc. ADSP-21587BBCZ-4B

Overview

ADSP-21587BBCZ-4B from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor, delivering 500 MHz per SHARC+ core and 500 MHz Arm Cortex-A5 operation. It features 5 Mb L1 SRAM per SHARC+ core (with parity), 256 kB L2 SRAM with ECC, and supports 32-/40-/64-bit floating-point arithmetic. Designed for high-performance audio and automotive signal processing, it integrates dual CAN 2.0 interfaces, USB 2.0 HS, PCIe 2.0 (1 lane), and hardware accelerators for FFT/IFFT, FIR/IIR, and SINC filtering.

For engineers reviewing the ADSP-21587BBCZ-4B datasheet, ADSP-21587BBCZ-4B pinout, ADSP-21587BBCZ-4B application, or ADSP-21587BBCZ-4B equivalent, key selection considerations include dual-core SHARC+ clock speed, L1/L2 memory configuration, automotive AEC-Q100 qualification, PCIe 2.0 support, and dual CAN 2.0 interface availability in the 529-ball BGA package.

Technical Context

The ADSP-21587BBCZ-4B implements a heterogeneous dual-processor architecture: two SHARC+ cores operate at up to 500 MHz each with independent 5 Mb L1 SRAM (configurable as SRAM or cache), while the Arm Cortex-A5 runs at 500 MHz with 32 kB L1 instruction and data caches plus 256 kB L2 cache with parity. The system fabric interconnects both domains via requester/completer ports and includes a shared 256 kB L2 SRAM with ECC and 512 kB L2 ROM.

It integrates safety-critical infrastructure including System Protection Unit (SPU), Dual CRC engines, watchdog timers, Thermal Monitor Unit (TMU), and Arm TrustZone security extensions. Peripheral subsystems include dual CAN 2.0 controllers, PCIe 2.0 (1 lane), two USB 2.0 HS PHYs, dual EMACs, SDIO/eMMC, and eight-channel 12-bit HADC - all mapped to the 529-ball CSP_BGA package with 0.8 mm pitch.

Key Specifications

Pinout & Package

ADSP-21587BBCZ-4B uses a 529-ball CSP_BGA package (19 mm × 19 mm, 0.8 mm pitch) with ball pitch compatible with standard surface-mount assembly processes. Pin assignments follow Analog Devices' standardized 529-ball CSP_BGA layout, supporting full I/O multiplexing across GPIO Ports A–G (102 + 40 DAI pins).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP + application processor applications.

Compared with ADSP-21587BBCZ-4B, ADSP-SC587WBCZ-4 trades PCIe for MLB audio transport in automotive contexts, while ADSP-21584BBCZ-4 reduces package size and peripheral count to lower cost-neither offers identical interface coverage, making ADSP-21587BBCZ-4B the only option with PCIe 2.0, dual USB 2.0 HS, and SDIO/eMMC in the 529-BGA form factor.

Availability

ADSP-21587BBCZ-4B is available at Aetrix Electronics and suitable for automotive audio gateways, professional digital mixers, industrial motor control gateways, and medical ultrasound beamformers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADSP-21587BBCZ-4B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision, power, and connectivity applications.

The ADSP-21587BBCZ-4B belongs to the SHARC+ dual-core DSP family with Arm Cortex-A5 integration, designed specifically for high-reliability, high-throughput signal processing in automotive, professional audio, and industrial edge systems demanding both real-time determinism and rich OS capabilities.

FAQ

What is the maximum operating frequency of each SHARC+ core in the ADSP-21587BBCZ-4B?

The ADSP-21587BBCZ-4B supports up to 500 MHz per SHARC+ core, as confirmed in the Rev. C datasheet Table 2. This frequency is achievable under specified operating conditions (VDD_INT = 1.0 V, junction temperature ≤105°C) and enables sustained 3000+ MFLOPS performance per core for floating-point workloads. The ADSP-21587BBCZ-4B must be operated within its validated voltage and thermal envelope to maintain this clock rate reliably.

Does the ADSP-21587BBCZ-4B include hardware support for secure boot and cryptographic acceleration?

Yes, the ADSP-21587BBCZ-4B includes dedicated cryptographic hardware accelerators and fast secure boot with IP protection, as documented in the "Security and Protection" section. It supports Arm TrustZone, enabling secure world execution, and integrates OTP memory for key storage. These features are silicon-verified and enabled via the Boot ROM and Security Configuration Unit (SCU) registers in the ADSP-21587BBCZ-4B.

Which package type and ball count does the ADSP-21587BBCZ-4B use?

The ADSP-21587BBCZ-4B uses a 529-ball CSP_BGA package with 0.8 mm pitch and 19 mm × 19 mm body size, as specified in the "Outline Dimensions" and "529-Ball CSP_BGA Signal Descriptions" sections. This package provides full access to all peripherals including PCIe, dual CAN, dual USB 2.0 HS, and SDIO/eMMC - unlike the 349-ball variants which omit several high-speed interfaces.

Is the ADSP-21587BBCZ-4B qualified for automotive applications?

Yes, the ADSP-21587BBCZ-4B is AEC-Q100 qualified for automotive applications (Grade 2, −40°C to +105°C ambient), as explicitly stated in the "Additional Features" and "Automotive Products" sections. This qualification covers HTOL, temperature cycling, ESD, and other stress tests required for under-hood and cabin ECUs, and applies to the exact ADSP-21587BBCZ-4B orderable part number.

What types of hardware accelerators are integrated into the ADSP-21587BBCZ-4B?

The ADSP-21587BBCZ-4B integrates a high-performance pipelined FFT/IFFT engine, FIR and IIR offload engines, a harmonic analysis engine (HAE), and a SINC filter accelerator - all documented in the "Additional Features" and "System Acceleration" sections. These accelerators operate independently of the SHARC+ cores and reduce latency for common signal processing kernels by offloading computation from the main DSP pipeline.