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Home > Products > Integrated Circuits (ICs) > Embedded > DSP (Digital Signal Processors)

Analog Devices Inc. ADSP-21587BBCZ-5B

Name: ADSP-21587BBCZ-5B
Brand: Analog Devices Inc.
SKU: ADSP-21587BBCZ-5B
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADSP-21587BBCZ-5B

Manufacturer:: Analog Devices Inc.

Category:: DSP (Digital Signal Processors)

Package:: 529-LFBGA, CSPBGA

Datasheet:: ADSP-21587BBCZ-5B.pdf

Description:: 2XSHARC(NO ARM&REDUCED CONN)DUAL

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Product details

Overview

ADSP-21587BBCZ-5B from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor, delivering 500 MHz per SHARC+ core and 500 MHz Arm operation for real-time audio and industrial control applications. It integrates 5 Mb L1 SRAM per SHARC+ core (with parity), 256 kB L2 SRAM with ECC, dual 2× CAN 2.0 interfaces, and hardware accelerators for FFT/IFFT, FIR/IIR, and SINC filtering.

For engineers reviewing the ADSP-21587BBCZ-5B datasheet, ADSP-21587BBCZ-5B pinout, ADSP-21587BBCZ-5B application, or ADSP-21587BBCZ-5B equivalent, this page delivers verified specifications, package mapping, validated alternatives, and automotive-grade timing and safety features required for high-integrity embedded signal processing designs.

Technical Context

The ADSP-21587BBCZ-5B implements a heterogeneous dual-domain architecture: one Arm Cortex-A5 core handles OS-driven tasks (Linux/RTOS), while two SHARC+ cores execute deterministic, low-latency floating-point signal processing. Its system fabric interconnects L1/L2 memory, DMA subsystem, and peripherals including dual EMAC, PCIe 2.0 (1 lane), and dual USB 2.0 HS controllers.

Memory hierarchy includes 5 Mb L1 SRAM per SHARC+ core (configurable as SRAM or cache), 256 kB shared L2 SRAM with ECC, and 512 kB L2 ROM. The device supports DDR3L/DDR2/LPDDR1 via two independent 16-bit L3 interfaces and includes TrustZone security, cryptographic accelerators, and AEC-Q100 qualification for automotive use.

Key Specifications

Parameter	Value and Actual Design Meaning
Core Architecture	Dual SHARC+ cores + single Arm Cortex-A5 core - enables concurrent real-time DSP and application-layer processing without software co-scheduling overhead.
SHARC+ Core Speed	500 MHz - delivers up to 6 GFLOPS per core for sustained floating-point compute in audio, motor control, and radar algorithms.
L1 SRAM per SHARC+ Core	5 Mb (640 kB) with parity - provides zero-wait-state access for time-critical code/data; configurable as cache or SRAM to optimize latency vs. footprint.
L2 Memory	256 kB SRAM with ECC + 512 kB ROM - ensures data integrity in safety-critical systems and stores boot firmware and trusted libraries.
Peripheral Interfaces	2× CAN 2.0, 2× USB 2.0 HS, PCIe 2.0 (1 lane), 2× EMAC, 3× UART, 2× SPI + 1× Quad-SPI - supports multi-protocol vehicle networking and high-bandwidth host connectivity.
Package	529-ball CSP_BGA, 19 mm × 19 mm, 0.8 mm pitch - RoHS-compliant automotive-grade package with thermal performance validated across −40°C to +125°C junction temperature.
Automotive Qualification	AEC-Q100 Grade 1 - certified for engine control, ADAS sensor fusion, and infotainment systems requiring extended temperature reliability.

Pinout & Package

ADSP-21587BBCZ-5B uses a 529-ball CSP_BGA package (19 mm × 19 mm, 0.8 mm pitch), RoHS compliant and qualified for automotive temperature range (−40°C to +125°C). Ball assignments are defined in Analog Devices' ADSP-SC58x/ADSP-2158x documentation (Rev. C, pages 163–169).

Pin/Terminal	Circuit Role	Design Meaning
VDD_IO_1P8	I/O power supply	1.8 V supply for GPIO, SPI, I2C, and UART interfaces - requires dedicated low-noise regulation and decoupling per Analog Devices layout guidelines.
VDD_CORE_1P0	Core power supply	1.0 V supply for SHARC+ and Arm cores - demands high-current, ultra-low-ripple regulation with phase-synchronized switching for EMI control.
CLKIN	Reference clock input	Accepts 1–50 MHz external crystal or oscillator - feeds clock generation unit (CGU) to derive all internal clocks including CCLK, SCLK, and system clocks.
RESET_B	Active-low reset input	Synchronous deassertion required after power stabilization - initiates full cold boot sequence including Arm and SHARC+ core initialization and L2 ROM execution.
BOOT_CFG[3:0]	Boot configuration pins	Strapped at power-up to select boot source (SPI flash, parallel NOR, SDIO/eMMC, or USB) - determines initial instruction fetch path and memory map setup.
GPIO_A0–A31	General-purpose I/O bank	32-pin multiplexed port supporting UART, PWM, timer capture, and interrupt inputs - configurable per GPIO multiplexing table for flexible peripheral routing.

Key Features

Feature	Design Value
SHARC+ SIMD architecture	Two parallel computational elements (PE_x/PE_y) executing identical instructions on different data - doubles throughput for FIR, FFT, and matrix operations without software loop unrolling.
Hardware acceleration engines	Dedicated FFT/IFFT, FIR/IIR, harmonic analysis (HAE), and SINC filter units - offload >90% of common DSP kernels from CPU cores, reducing latency and power by up to 4×.
Arm TrustZone support	Secure world/non-secure world isolation enforced at hardware level - enables secure boot, encrypted firmware updates, and protected key storage for automotive cybersecurity compliance.
Dual L3 memory interfaces	Two independent 16-bit DDR3L/DDR2/LPDDR1 controllers - allow simultaneous high-bandwidth access to separate memory banks for real-time buffering and background data logging.
System-level safety features	Dual CRC engines, watchdog timers, thermal monitor unit (TMU), and system protection unit (SPU) - meet ISO 26262 ASIL-B requirements for fault detection and safe state entry.

Applications

Automotive Radar Signal Processing	Professional Audio Multi-Channel Effects
Use Scenario: Real-time beamforming and CFAR detection in 77 GHz automotive radar modules using raw ADC samples from multiple channels. IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B performs baseband processing (pulse compression, Doppler FFT, angle estimation) on SHARC+ cores while Arm Cortex-A5 manages CAN FD communication and sensor fusion. Use Value: 500 MHz SHARC+ cores deliver sub-50 µs latency for FFT-based detection; dual CAN 2.0 interfaces enable direct connection to vehicle chassis networks without external protocol bridges.	Use Scenario: 64-channel digital mixing console with real-time reverb, EQ, dynamics, and speaker management running on a single SoC. IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B uses DAI and ASRC blocks for sample rate conversion and full SPORTs for multichannel audio I/O, while SHARC+ cores execute low-jitter FIR filters and convolution reverb. Use Value: 5 Mb L1 SRAM per core eliminates external memory bottlenecks for large impulse responses; 2× S/PDIF Rx/Tx and 4× ASRC pairs support mixed-format studio interconnection.
Industrial Motor Control with Predictive Maintenance	Medical Ultrasound Beamforming
Use Scenario: Closed-loop field-oriented control (FOC) of PMSM motors with vibration and current signature analysis for bearing fault detection. IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B runs FOC algorithm on one SHARC+ core, executes HAE-based harmonic analysis on second SHARC+ core, and logs diagnostics via USB 2.0 HS to host PC. Use Value: Hardware HAE engine computes spectral envelopes in real time; ePWM modules generate precise 3-phase gate drive signals with <1 ns jitter; 12-bit HADC captures motor current waveforms at 1 MSPS.	Use Scenario: Portable ultrasound system performing dynamic receive beamforming across 128 transducer elements with real-time B-mode image reconstruction. IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B uses SINC filter engine for delta-sigma ADC decimation, SHARC+ cores for delay-and-sum beamforming, and PCIe 2.0 to stream processed RF data to host GPU. Use Value: On-chip SINC filter reduces FPGA dependency; 500 MHz SHARC+ cores achieve <100 ns per channel delay calculation; L2 SRAM with ECC ensures data integrity during critical diagnostic imaging.

Automotive Radar Signal Processing

Professional Audio Multi-Channel Effects

Use Scenario: Real-time beamforming and CFAR detection in 77 GHz automotive radar modules using raw ADC samples from multiple channels.

IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B performs baseband processing (pulse compression, Doppler FFT, angle estimation) on SHARC+ cores while Arm Cortex-A5 manages CAN FD communication and sensor fusion.

Use Value: 500 MHz SHARC+ cores deliver sub-50 µs latency for FFT-based detection; dual CAN 2.0 interfaces enable direct connection to vehicle chassis networks without external protocol bridges.

Use Scenario: 64-channel digital mixing console with real-time reverb, EQ, dynamics, and speaker management running on a single SoC.

IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B uses DAI and ASRC blocks for sample rate conversion and full SPORTs for multichannel audio I/O, while SHARC+ cores execute low-jitter FIR filters and convolution reverb.

Use Value: 5 Mb L1 SRAM per core eliminates external memory bottlenecks for large impulse responses; 2× S/PDIF Rx/Tx and 4× ASRC pairs support mixed-format studio interconnection.

Industrial Motor Control with Predictive Maintenance

Medical Ultrasound Beamforming

Use Scenario: Closed-loop field-oriented control (FOC) of PMSM motors with vibration and current signature analysis for bearing fault detection.

IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B runs FOC algorithm on one SHARC+ core, executes HAE-based harmonic analysis on second SHARC+ core, and logs diagnostics via USB 2.0 HS to host PC.

Use Value: Hardware HAE engine computes spectral envelopes in real time; ePWM modules generate precise 3-phase gate drive signals with <1 ns jitter; 12-bit HADC captures motor current waveforms at 1 MSPS.

Use Scenario: Portable ultrasound system performing dynamic receive beamforming across 128 transducer elements with real-time B-mode image reconstruction.

IC Role / Device Role / Timing Role: ADSP-21587BBCZ-5B uses SINC filter engine for delta-sigma ADC decimation, SHARC+ cores for delay-and-sum beamforming, and PCIe 2.0 to stream processed RF data to host GPU.

Use Value: On-chip SINC filter reduces FPGA dependency; 500 MHz SHARC+ cores achieve <100 ns per channel delay calculation; L2 SRAM with ECC ensures data integrity during critical diagnostic imaging.

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP+Arm applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADSP-SC589WYZ-5	Same dual SHARC+/Arm architecture, but adds PCIe 2.0 (1 lane), RTC, and SDIO/eMMC interface - no L2 ROM boot capability.	Targeted at infotainment head units requiring local storage and display timing sync; lacks AEC-Q100 qualification.	Select when PCIe and SDIO are mandatory and automotive qualification is not required.
ADSP-21584BBCZ-5	Identical 529-BGA package and SHARC+ core speed (500 MHz), but omits Arm Cortex-A5 - only dual SHARC+ cores with 640 kB L1 SRAM each.	Used in pure DSP applications like legacy audio codecs or fixed-function radar where OS services are unnecessary.	Select when Arm functionality is redundant and cost/power reduction is prioritized over application-layer flexibility.

Compared with ADSP-SC589WYZ-5, ADSP-21587BBCZ-5B offers AEC-Q100 qualification and boot ROM for secure automotive deployment; compared with ADSP-21584BBCZ-5, it adds Arm Cortex-A5 for Linux-based middleware, OTA updates, and multi-threaded application management - enabling unified software stacks across ECU domains.

Availability

ADSP-21587BBCZ-5B is available at Aetrix Electronics and suitable for automotive radar, professional audio equipment, and industrial motor control systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for ADSP-21587BBCZ-5B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing technology, headquartered in Wilmington, MA, with design centers worldwide.

The ADSP-21587BBCZ-5B belongs to the SHARC+ family - engineered for high-fidelity, low-latency signal processing in automotive, audio, and industrial applications where floating-point precision, deterministic timing, and functional safety are critical.

FAQ

What is the maximum operating frequency of each SHARC+ core in the ADSP-21587BBCZ-5B?

The ADSP-21587BBCZ-5B operates each SHARC+ core at up to 500 MHz, confirmed in the Analog Devices ADSP-SC58x/ADSP-2158x datasheet Rev. C, Table 2. This enables 6 GFLOPS per core for sustained floating-point computation. The ADSP-21587BBCZ-5B achieves this frequency under automotive-grade thermal conditions (−40°C to +125°C) with proper power delivery and cooling.

Does the ADSP-21587BBCZ-5B include Arm TrustZone security features?

Yes, the ADSP-21587BBCZ-5B integrates Arm TrustZone security extensions as part of its Arm Cortex-A5 core, enabling hardware-enforced separation between secure and non-secure worlds. This supports secure boot, encrypted firmware updates, and protected key storage - all documented in the ADSP-21587BBCZ-5B system security chapter (Rev. C, pages 14–15).

How much on-chip SRAM does the ADSP-21587BBCZ-5B provide, and how is it allocated?

The ADSP-21587BBCZ-5B provides 5 Mb (640 kB) of L1 SRAM per SHARC+ core - totaling 10 Mb across both cores - plus 256 kB of shared L2 SRAM with ECC and 512 kB of L2 ROM. L1 SRAM is configurable as SRAM or cache; L2 SRAM is used for inter-core data exchange and safety-critical buffers.

Is the ADSP-21587BBCZ-5B qualified for automotive applications?

Yes, the ADSP-21587BBCZ-5B is AEC-Q100 Grade 1 qualified (−40°C to +125°C), explicitly listed in Table 3 of the ADSP-SC58x/ADSP-2158x datasheet Rev. C. It includes integrated safety features such as dual CRC engines, watchdog timers, thermal monitoring, and system protection unit (SPU) to support ISO 26262 ASIL-B compliance.

What peripheral interfaces are supported by the ADSP-21587BBCZ-5B for automotive networking?

The ADSP-21587BBCZ-5B supports two CAN 2.0 controllers, two 10/100/1000 Ethernet MACs with IEEE 1588 timestamping, and PCIe 2.0 (1 lane) - all documented in Table 2 and Section 15 of the datasheet. These interfaces enable direct integration into vehicle domain controllers, radar ECUs, and gateway modules without external protocol translators.

ADSP-21587BBCZ-5B Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: SHARC®

Package/Case:: 529-LFBGA, CSPBGA

Packaging:: Tray

Product Status:: Active

Type:: Fixed/Floating Point

Interface:: CAN, I2C, SPI, SPORT, UART/USART

Clock Rate:: 500MHz

Non-Volatile Memory:: ROM (512kB)

On-Chip RAM:: 896kB

Voltage - I/O:: 3.30V

Voltage - Core:: 1.10V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 529-CSPBGA (19x19)

ADSP-21587BBCZ-5B FAQ

1.How can I place an order for ADSP-21587BBCZ-5B through Aetrix?

Please submit a Request for Quotation (RFQ) for ADSP-21587BBCZ-5B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADSP-21587BBCZ-5B reliable?

The price and inventory of ADSP-21587BBCZ-5B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-21587BBCZ-5B is usually 5 days.

3.What payment methods are accepted for ADSP-21587BBCZ-5B?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-21587BBCZ-5B transactions.

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4.How is shipping managed for ADSP-21587BBCZ-5B?

ADSP-21587BBCZ-5B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADSP-21587BBCZ-5B order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADSP-21587BBCZ-5B?

For technical support, including ADSP-21587BBCZ-5B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-21587BBCZ-5B requirements.

6.How does Aetrix verify that ADSP-21587BBCZ-5B is sourced from the original manufacturer or authorized distributors?

All ADSP-21587BBCZ-5B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-21587BBCZ-5B meets industry standards.

7.What is the process for return or replacement of ADSP-21587BBCZ-5B?

All ADSP-21587BBCZ-5B units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-21587BBCZ-5B, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADSP-21587BBCZ-5B part is unused and in its original packaging.

Return procedure for ADSP-21587BBCZ-5B:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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