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Home > Products > Integrated Circuits (ICs) > Embedded > DSP (Digital Signal Processors)

Analog Devices Inc. ADSP-21587KBCZ-5B

Name: ADSP-21587KBCZ-5B
Brand: Analog Devices Inc.
SKU: ADSP-21587KBCZ-5B
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADSP-21587KBCZ-5B

Manufacturer:: Analog Devices Inc.

Category:: DSP (Digital Signal Processors)

Package:: 529-LFBGA, CSPBGA

Datasheet:: ADSP-21587KBCZ-5B.pdf

Description:: 2XSHARC(NO ARM&REDUCED CONN)DUAL

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Product details

Overview

ADSP-21587KBCZ-5B from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor, delivering 500 MHz per SHARC+ core and 500 MHz Arm Cortex-A5 operation. It features 5 Mb L1 SRAM per SHARC+ core (with parity), 256 kB L2 SRAM with ECC, and dual 16-bit DDR3/DDR2/LPDDR1 interfaces. Used in automotive infotainment and professional audio systems requiring deterministic real-time signal processing and application-level OS support.

For engineers reviewing the ADSP-21587KBCZ-5B datasheet, ADSP-21587KBCZ-5B pinout, ADSP-21587KBCZ-5B application, or ADSP-21587KBCZ-5B equivalent, key selection considerations include dual-core SHARC+ floating-point throughput, Arm Cortex-A5 Linux-capable subsystem integration, AEC-Q100 qualification, PCIe 2.0 (1-lane) support, and 529-ball CSP_BGA package compatibility with thermal and safety-critical system requirements.

Technical Context

The ADSP-21587KBCZ-5B implements a heterogeneous dual-domain architecture: one Arm Cortex-A5 core (500 MHz, NEON/VFPv4-D16, 32 kB I-cache/32 kB D-cache, 256 kB L2 cache with parity) and two SHARC+ cores (500 MHz each, 32-/40-/64-bit floating-point, 5 Mb L1 SRAM per core). The cores share a coherent system fabric with L2 SRAM (256 kB, ECC-protected) and L2 ROM (512 kB).

It integrates dedicated hardware accelerators including pipelined FFT/IFFT, FIR/IIR, harmonic analysis engine (HAE), SINC filter, cryptographic engines, and ASRCs (4 pairs), all accessible via DMA-controlled data paths. System-level safety is enforced through integrated SPU, dual CRC, watchdogs, TMU, and Arm TrustZone security extensions.

Key Specifications

Parameter	Value and Actual Design Meaning
Core Architecture	Dual SHARC+ (500 MHz) + Arm Cortex-A5 (500 MHz), instruction-set compatible with ADSP-214xx/213xx SHARC families
L1 Memory per SHARC+	5 Mb (640 kB) SRAM with parity; configurable as cache or tightly coupled memory for single-cycle access
L2 Memory	256 kB SRAM with ECC protection + 512 kB ROM; shared across all cores for boot and system code storage
Memory Interfaces	Dual 16-bit DDR3/DDR2/LPDDR1 controllers; supports 1.5 V DDR3L, LPDDR1, and legacy DDR2 devices
Peripheral Integration	2× CAN 2.0, 2× USB 2.0 HS (Host/Device), PCIe 2.0 (1 lane), 2× EMAC (10/100/1000 + IEEE 1588), 8-channel 12-bit HADC, SDIO/eMMC
Package & Thermal	529-ball CSP_BGA, 19 mm × 19 mm, 0.8 mm pitch, RoHS compliant; AEC-Q100 qualified for automotive temperature range (−40°C to +125°C)
Security & Safety	Arm TrustZone, cryptographic hardware accelerators, fast secure boot with IP protection, integrated SPU, dual CRC, watchdog timers, thermal monitor unit (TMU)

Pinout & Package

ADSP-21587KBCZ-5B uses a 529-ball CSP_BGA package (19 mm × 19 mm, 0.8 mm pitch), RoHS compliant, with ball assignments defined in Analog Devices Document Rev. C (pages 163–169). Pin functions are multiplexed across GPIO Ports A–G and dedicated peripheral signals (e.g., DDR_DQ[15:0], USB_DP/DM, PCIe_REFCLK, CAN_RX/TX, EMAC_MDIO/MDC).

Pin/Terminal	Circuit Role	Design Meaning
VDD_DDR	Power supply	1.5 V supply for DDR interface; requires low-noise regulation and local decoupling
DDR_DQ[15:0]	Data bus	16-bit bidirectional data lines for DDR3/DDR2/LPDDR1; routed with matched length and controlled impedance
USB_DP / USB_DM	Differential I/O	Full-speed/high-speed USB 2.0 differential pair; requires 90 Ω differential impedance and ESD protection
PCIE_REFCLK_P/N	Clock input	100 MHz differential reference clock for PCIe PHY; must meet jitter and skew specifications per PCIe 2.0
CAN0_RX / CAN0_TX	Transceiver interface	Dedicated CAN 2.0B physical layer signals; require external transceiver and common-mode choke
HADC_IN[7:0]	Analog input	8-channel 12-bit SAR ADC inputs; routed away from digital switching noise and with guard traces

Key Features

Feature	Design Value
Dual SHARC+ + Arm Cortex-A5 heterogeneity	Enables concurrent real-time DSP (SHARC+) and application-layer OS tasks (Linux on Cortex-A5) without inter-core latency penalties
Hardware-accelerated FFT/IFFT engine	Offloads up to 1024-point complex FFTs at full SHARC+ clock rate, freeing CPU cycles for control logic and I/O management
AEC-Q100 Grade 2 qualification	Validated for automotive under-hood and infotainment applications operating from −40°C to +105°C ambient (junction up to +125°C)
Integrated SPU and TrustZone	Provides hardware-enforced memory isolation between secure boot firmware, safety-critical SHARC+ tasks, and non-secure Cortex-A5 applications
Dual DDR controller with LPDDR1 support	Enables low-power memory expansion for audio buffer streaming while maintaining deterministic latency for SHARC+ real-time processing

Applications

Automotive Infotainment Head Unit	Professional Digital Audio Workstation
Use Scenario: Real-time multi-zone audio processing, voice recognition, navigation rendering, and Android Automotive OS execution in a single SoC. IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B serves as the central compute hub-SHARC+ cores handle echo cancellation, beamforming, and Dolby decoding; Cortex-A5 runs Android framework and UI stack. Use Value: Eliminates inter-processor communication bottlenecks; DDR bandwidth is partitioned between SHARC+ audio buffers and Cortex-A5 OS memory, ensuring sub-10 ms audio latency and responsive GUI.	Use Scenario: High-channel-count studio mixer with real-time effects (reverb, EQ, dynamics), sample-accurate synchronization, and DAW host communication. IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B acts as the primary DSP engine-SHARC+ cores execute low-latency FIR filters and ASRCs; Cortex-A5 manages USB 2.0 audio class drivers and Ethernet AVB transport. Use Value: Dual SHARC+ cores deliver >2 GFLOPS sustained floating-point performance for 96 kHz/24-bit 64-channel processing; PCIe 2.0 enables direct FPGA co-processing for custom I/O expansion.
Industrial Motor Drive Controller	Medical Ultrasound Beamformer
Use Scenario: Closed-loop servo control with field-oriented control (FOC), predictive maintenance analytics, and HMI display on a single board. IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B executes FOC algorithms on SHARC+ cores with <500 ns interrupt latency; Cortex-A5 runs Linux-based diagnostics and web server. Use Value: Integrated ePWM modules (3×) and HADC (8 ch, 12-bit) enable direct motor phase sensing and gate drive timing; safety features (SPU, dual CRC) support SIL-2 functional safety compliance.	Use Scenario: Portable ultrasound system requiring real-time beamforming, RF echo processing, and DICOM image export over Gigabit Ethernet. IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B performs channel-wise FIR filtering and dynamic receive focusing on SHARC+ cores; Cortex-A5 handles TCP/IP stack, JPEG compression, and touchscreen interface. Use Value: SINC filter engine accelerates analog front-end digitization; dual EMAC with IEEE 1588 enables synchronized multi-probe acquisition; 256 kB L2 SRAM stores time-aligned RF samples for synthetic aperture reconstruction.

Automotive Infotainment Head Unit

Professional Digital Audio Workstation

Use Scenario: Real-time multi-zone audio processing, voice recognition, navigation rendering, and Android Automotive OS execution in a single SoC.

IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B serves as the central compute hub-SHARC+ cores handle echo cancellation, beamforming, and Dolby decoding; Cortex-A5 runs Android framework and UI stack.

Use Value: Eliminates inter-processor communication bottlenecks; DDR bandwidth is partitioned between SHARC+ audio buffers and Cortex-A5 OS memory, ensuring sub-10 ms audio latency and responsive GUI.

Use Scenario: High-channel-count studio mixer with real-time effects (reverb, EQ, dynamics), sample-accurate synchronization, and DAW host communication.

IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B acts as the primary DSP engine-SHARC+ cores execute low-latency FIR filters and ASRCs; Cortex-A5 manages USB 2.0 audio class drivers and Ethernet AVB transport.

Use Value: Dual SHARC+ cores deliver >2 GFLOPS sustained floating-point performance for 96 kHz/24-bit 64-channel processing; PCIe 2.0 enables direct FPGA co-processing for custom I/O expansion.

Industrial Motor Drive Controller

Medical Ultrasound Beamformer

Use Scenario: Closed-loop servo control with field-oriented control (FOC), predictive maintenance analytics, and HMI display on a single board.

IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B executes FOC algorithms on SHARC+ cores with <500 ns interrupt latency; Cortex-A5 runs Linux-based diagnostics and web server.

Use Value: Integrated ePWM modules (3×) and HADC (8 ch, 12-bit) enable direct motor phase sensing and gate drive timing; safety features (SPU, dual CRC) support SIL-2 functional safety compliance.

Use Scenario: Portable ultrasound system requiring real-time beamforming, RF echo processing, and DICOM image export over Gigabit Ethernet.

IC Role / Device Role / Timing Role: ADSP-21587KBCZ-5B performs channel-wise FIR filtering and dynamic receive focusing on SHARC+ cores; Cortex-A5 handles TCP/IP stack, JPEG compression, and touchscreen interface.

Use Value: SINC filter engine accelerates analog front-end digitization; dual EMAC with IEEE 1588 enables synchronized multi-probe acquisition; 256 kB L2 SRAM stores time-aligned RF samples for synthetic aperture reconstruction.

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP+application processor applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADSP-SC589KBCZ-5	Same dual SHARC+/Cortex-A5 architecture, but adds PCIe 2.0 (1 lane), RTC, and additional GPIO (Port G); identical 529-BGA package and pinout	Supports time-stamped logging and PCIe-based FPGA offload; preferred when RTC or extended I/O is required	Select ADSP-SC589KBCZ-5 if PCIe endpoint functionality or real-time clock is mandatory; otherwise ADSP-21587KBCZ-5B offers identical DSP performance at lower BOM cost
ADSP-21584KBCZ-5	Shares same SHARC+ core speed (500 MHz) and L1 SRAM (640 kB), but lacks Arm Cortex-A5; uses 349-BGA package (19 mm × 19 mm, 0.8 mm pitch)	Targeted at pure DSP workloads without OS requirements; no Linux support, reduced peripheral set (no USB, PCIe, EMAC)	Choose ADSP-21584KBCZ-5 only for cost-sensitive, standalone DSP designs where application-layer processing is handled externally

Compared with ADSP-SC589KBCZ-5, ADSP-21587KBCZ-5B omits RTC and one EMAC but retains full PCIe 2.0 and dual EMAC capability; versus ADSP-21584KBCZ-5, it adds Arm Cortex-A5 programmability and full peripheral richness at the cost of higher power and software complexity.

Availability

ADSP-21587KBCZ-5B is available at Aetrix Electronics and suitable for automotive infotainment, professional audio equipment, industrial motor control, and medical imaging systems requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant silicon.

Supply support for ADSP-21587KBCZ-5B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision, power, and connectivity applications.

The ADSP-21587KBCZ-5B belongs to the SHARC+ family, designed specifically for demanding real-time audio, industrial, and automotive applications requiring both deterministic floating-point computation and application-level OS capabilities in a single chip.

FAQ

What is the maximum operating frequency of each core in the ADSP-21587KBCZ-5B?

The ADSP-21587KBCZ-5B operates with two SHARC+ cores each running at up to 500 MHz and one Arm Cortex-A5 core also rated at 500 MHz. These frequencies are guaranteed across the full automotive temperature range (−40°C to +125°C junction) and supported by the 529-ball CSP_BGA thermal design. All core clocks derive from the on-chip CGU with programmable PLL dividers.

Does the ADSP-21587KBCZ-5B support DDR3L memory?

Yes, the ADSP-21587KBCZ-5B supports DDR3L memory through its dual 16-bit DDR3/DDR2/LPDDR1 controllers. The VDD_DDR supply is specified at 1.5 V, matching DDR3L voltage requirements. Timing parameters and electrical characteristics for DDR3L operation are fully documented in the Rev. C datasheet (pages 89–152), including tRCD, tRP, and tRFC values validated for 1.5 V operation.

Is the ADSP-21587KBCZ-5B pin-compatible with other ADSP-2158x series devices?

No, the ADSP-21587KBCZ-5B uses a 529-ball CSP_BGA package and is not pin-compatible with 349-ball variants like ADSP-21583KBCZ-5 or ADSP-21584KBCZ-5. However, it shares identical ball mapping and signal definitions with ADSP-SC587KBCZ-5 and ADSP-SC589KBCZ-5 within the 529-BGA footprint, enabling PCB reuse across those specific models.

What safety and security features are implemented in the ADSP-21587KBCZ-5B?

The ADSP-21587KBCZ-5B includes integrated safety and security features: Arm TrustZone for hardware-isolated secure world execution, System Protection Unit (SPU) for memory region access control, dual CRC engines for data integrity verification, watchdog timers with independent clock domains, thermal monitor unit (TMU), and cryptographic accelerators supporting AES, SHA, and RSA. These are documented in Sections 14–15 of the Rev. C datasheet.

Which development tools are officially supported for the ADSP-21587KBCZ-5B?

Analog Devices officially supports CrossCore Embedded Studio (CCES) v2.12.0+ for ADSP-21587KBCZ-5B firmware development, including SHARC+ assembly/C optimization, Cortex-A5 bare-metal and Linux BSPs, and debug via JTAG/SWD. Hardware evaluation is enabled by the ADZS-SC589-EZKIT and ADZS-21587-EZBRD reference boards, both featuring full pin access, DDR3 memory, and USB/PCIe connectivity.

ADSP-21587KBCZ-5B Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: SHARC®

Package/Case:: 529-LFBGA, CSPBGA

Packaging:: Tray

Product Status:: Active

Type:: Floating Point

Interface:: CAN, EBI/EMI, Ethernet, DAI, I2C, MMC/SD/SDIO, SPI, SPORT, UART/USART, USB OTG

Clock Rate:: 500MHz

Non-Volatile Memory:: ROM (512kB)

On-Chip RAM:: 640kB

Voltage - I/O:: 3.30V

Voltage - Core:: 1.10V

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 529-CSPBGA (19x19)

ADSP-21587KBCZ-5B FAQ

1.How can I place an order for ADSP-21587KBCZ-5B through Aetrix?

Please submit a Request for Quotation (RFQ) for ADSP-21587KBCZ-5B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADSP-21587KBCZ-5B reliable?

The price and inventory of ADSP-21587KBCZ-5B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-21587KBCZ-5B is usually 5 days.

3.What payment methods are accepted for ADSP-21587KBCZ-5B?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-21587KBCZ-5B transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADSP-21587KBCZ-5B?

ADSP-21587KBCZ-5B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADSP-21587KBCZ-5B order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADSP-21587KBCZ-5B?

For technical support, including ADSP-21587KBCZ-5B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-21587KBCZ-5B requirements.

6.How does Aetrix verify that ADSP-21587KBCZ-5B is sourced from the original manufacturer or authorized distributors?

All ADSP-21587KBCZ-5B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-21587KBCZ-5B meets industry standards.

7.What is the process for return or replacement of ADSP-21587KBCZ-5B?

All ADSP-21587KBCZ-5B units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-21587KBCZ-5B, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADSP-21587KBCZ-5B part is unused and in its original packaging.

Return procedure for ADSP-21587KBCZ-5B:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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