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Analog Devices Inc. ADSP-2173BST-80
- Part No.:
- ADSP-2173BST-80
- Manufacturer:
- Analog Devices Inc.
- Category:
- DSP (Digital Signal Processors)
- Package:
- 128-LQFP
- Datasheet:
-
ADSP-2173BST-80.pdf
- Description:
- IC DSP CONTROLLER 16BIT 128TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:198
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Product details
Overview
ADSP-2173BST-80 from Analog Devices is a 3.3 V, 50 ns instruction cycle (20 MIPS) fixed-point DSP microcomputer with dual serial ports, 8-bit/16-bit host interface port, 2K × 24-bit program RAM, 2K × 16-bit data RAM, and powerdown mode consuming only 0.36 mW standby. It executes single-cycle instructions while concurrently handling serial I/O, timer operations, and host communication-used in portable audio codecs and battery-powered voice processing systems.
For engineers reviewing the ADSP-2173BST-80 datasheet, ADSP-2173BST-80 pinout, ADSP-2173BST-80 application, or ADSP-2173BST-80 equivalent, key selection criteria include 3.3 V operation, 128-pin TQFP package, on-chip memory configuration, HIP bus width configurability, and verified powerdown recovery timing of 100 CLKIN cycles.
Technical Context
The ADSP-2173BST-80 implements the ADSP-2100 base architecture with three independent computational units (ALU, MAC, shifter), two dedicated DAGs, and zero-overhead looping. It supports bit manipulation instructions (set/clear/toggle/test), biased rounding, global interrupt masking, and Bus Grant Hang Logic (BGH) for external bus arbitration.
Its memory subsystem includes dual-purpose program memory (instruction/data storage), programmable wait-state generation, and automatic booting from byte-wide EPROM or via the host interface port. The 16-bit interval timer uses TSCALE/TCOUNT/TPERIOD registers for precise periodic interrupts, and SPORT0 supports multichannel TDM with 24/32-word frame handling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Instruction Cycle Time | 50 ns at 3.3 V - enables 20 MIPS sustained throughput with full parallel execution of address generation, data moves, and computation |
| Supply Voltage | 3.3 V ± 0.3 V - defines system-level power rail requirement and eliminates need for 5 V regulation in portable designs |
| On-Chip Program Memory | 2K × 24-bit RAM - provides executable code space without external PROM; supports dynamic reconfiguration and runtime loading |
| On-Chip Data Memory | 2K × 16-bit RAM - delivers dual-operand fetch capability per cycle when paired with program memory access |
| Standby Power Dissipation | 0.36 mW - measured in CMOS powerdown mode with 100-cycle recovery, critical for battery life in always-on voice wake-up systems |
| Host Interface Width | Configurable 8-bit or 16-bit - determined by HSIZE pin; enables direct interfacing to 80C51 or 68000-series hosts without glue logic |
| Serial Ports | Two independent SPORTs - each with double-buffered Tx/Rx, hardware A-law/μ-law companding, and frame sync flexibility for telephony interfaces |
Pinout & Package
The ADSP-2173BST-80 is housed in a 128-lead thin quad flat package (TQFP) with 0.4 mm lead pitch, thermally enhanced for embedded signal processing applications requiring compact PCB layout and moderate power dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN/XTAL | Clock input | Accepts 10 MHz crystal or TTL clock; internal oscillator enables low-jitter timing without external PLL |
| PWD | Powerdown control | Active-low hardware entry into 0.36 mW standby mode; synchronized with internal state machines to prevent corruption |
| HSEL, HSIZE, BMODE | Host interface configuration | Set HIP operating mode (8/16-bit), boot source (EPROM vs. HIP), and address/data multiplexing at reset |
| SPORT0 (TFS0, RFS0, DT0, DR0, SCLK0) | Synchronous serial interface | Full-duplex TDM-capable port supporting 3–16-bit words, frame sync polarity inversion, and internal clock generation |
| FL2–0 | General-purpose flag outputs | Software-controllable status signals for external event notification (e.g., codec ready, buffer full) |
| IRQ0/IRQ1 (reconfigurable on SPORT1) | External interrupt inputs | Edge- or level-sensitive; allow SPORT1 pins to serve as dual-purpose I/O or interrupt sources without pin count penalty |
Key Features
| Feature | Design Value |
|---|---|
| Single-cycle instruction execution | Every instruction completes in one 50 ns cycle-including multifunction ops (data move + ALU), enabling deterministic real-time response |
| Dual DAG architecture | Two independent address generators maintain four pointers each with modulo addressing, enabling efficient circular buffer management for FIR/IIR filters |
| Bus Grant Hang Logic (BGH) | Prevents bus lockup during external memory access by holding BG active until current transfer completes, ensuring reliable co-processor arbitration |
| Programmable slow idle mode | IDLE(n) instruction with n = 16/32/64/128 reduces internal clock proportionally-slows timer/SCLK but retains full interrupt latency predictability |
| Automatic boot from byte-wide EPROM | Loads internal program RAM after reset using only 7 wait states-enables use of standard 200 ns EPROMs (e.g., 27C256) without speed-grade premium |
Applications
| Voice Codec Interface | Portable Audio Processing |
|---|---|
Use Scenario: Real-time A-law companded audio stream between ADSP-2173BST-80 and TI TLV320AIC10 codec over SPORT0. IC Role / Device Role / Timing Role: Primary DSP controller executing echo cancellation and DTMF detection; SPORT0 provides frame-synced 8-bit μ-law transfers at 8 kHz sampling rate. Use Value: Hardware companding offloads CPU cycles; 50 ns cycle time ensures sub-100 μs loop latency for acoustic echo suppression convergence. | Use Scenario: Battery-powered handheld speech recorder with flash storage and mono microphone preamp. IC Role / Device Role / Timing Role: Standalone signal processor managing ADC capture, FIR filtering, MP3 encoding prep, and SPI flash write sequencing. Use Value: 0.36 mW powerdown mode extends recording time >12 hrs on two AA cells; 2K data RAM buffers 1.5 sec of 16-bit/16 kHz audio before compression. |
| Industrial Sensor Fusion Hub | Legacy Bus Bridge Controller |
Use Scenario: Vibration monitoring node aggregating data from 4-channel sigma-delta ADCs and temperature sensors. IC Role / Device Role / Timing Role: Real-time preprocessing unit performing RMS calculation, spectral analysis, and alarm thresholding before CAN transmission. Use Value: Dual SPORTs handle simultaneous ADC daisy-chain streams; 20 MIPS throughput sustains 4× 24-bit FFTs/sec at 1 kHz update rate. | Use Scenario: Retrofit controller translating Modbus RTU commands from RS-485 to proprietary 8-bit parallel sensor interface. IC Role / Device Role / Timing Role: Protocol converter using HIP as 16-bit memory-mapped peripheral to host ARM9; SPORT1 handles RS-485 UART emulation via bit-banged framing. Use Value: Configurable HSIZE/BMODE pins enable plug-and-play integration with legacy 80C51-based HMIs; no FPGA or ASIC required. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-point DSP microcomputer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADSP-2172BSTZ-80 | 5 V supply, includes 8K × 24-bit on-chip ROM; no 3.3 V support | Requires 5 V rail; suited for mains-powered systems where ROM-based boot eliminates external EPROM | Select only if 5 V operation and ROM persistence are mandatory; not drop-in compatible due to voltage and memory architecture mismatch |
| TMS320VC5402PGE | 1.8 V core / 3.3 V I/O, 100 MIPS, 32K × 16-bit RAM; Harvard architecture with separate program/data buses | Higher performance but larger footprint (144-pin LQFP); lacks integrated HIP and dual SPORT TDM mode | Choose for bandwidth-intensive applications like wideband audio; requires redesign of memory map and interrupt handling |
Compared with ADSP-2172BSTZ-80 and TMS320VC5402PGE, the ADSP-2173BST-80 uniquely balances ultra-low 3.3 V standby power, integrated host interface, and TDM-ready serial ports-making it optimal for space-constrained, battery-operated voice edge nodes where boot flexibility and interrupt determinism outweigh raw MIPS.
Availability
ADSP-2173BST-80 is available at Aetrix Electronics and suitable for portable audio processing, industrial sensor fusion, and legacy bus bridge applications requiring stable component supply and long-term lifecycle assurance.
Supply support for ADSP-2173BST-80 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies since 1965.
The ADSP-217x product line was engineered for cost-sensitive, low-power digital signal processing in portable and embedded systems-emphasizing single-cycle determinism, integrated peripherals, and flexible memory booting.
FAQ
What is the maximum clock frequency supported by the ADSP-2173BST-80?
The ADSP-2173BST-80 operates with a 50 ns instruction cycle time, corresponding to a 10 MHz crystal or external clock input. Its internal instruction rate is 20 MIPS. The device does not support frequencies beyond 10 MHz input-exceeding this violates AC timing specifications and risks metastability in address/data latching.
Does the ADSP-2173BST-80 include on-chip program ROM?
No, the ADSP-2173BST-80 contains 2K × 24-bit on-chip program RAM and 2K × 16-bit data RAM only. Unlike the ADSP-2172, it omits the 8K × 24-bit program ROM. Boot code must be loaded externally via EPROM or through the host interface port at startup.
Can the ADSP-2173BST-80 execute code directly from external memory?
Yes, the ADSP-2173BST-80 supports external program memory execution using PMS, RD, and WR signals. However, all instructions must first be loaded into on-chip program RAM during boot unless configured for stand-alone ROM execution-a mode not implemented in the ADSP-2173 variant per its datasheet.
How many external interrupts does the ADSP-2173BST-80 support, and how are they configured?
The ADSP-2173BST-80 supports up to three external interrupts: IRQ0 and IRQ1 (reconfigurable on SPORT1 pins) and dedicated IRQ2. Each can be set edge- or level-sensitive via ICNTL register bits. All are individually maskable in IMASK except the non-maskable powerdown interrupt.
Is the ADSP-2173BST-80 pin-compatible with other ADSP-217x variants?
Yes, the ADSP-2173BST-80 shares identical 128-pin TQFP pinout with ADSP-2171BST-80 and ADSP-2172BST-80. However, voltage tolerance differences (3.3 V vs. 5 V) and absence of on-chip ROM in the ADSP-2173BST-80 require careful review of power supply and boot circuitry before substitution.
ADSP-2173BST-80 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- ADSP-21xx
- Package/Case:
- 128-LQFP
- Packaging:
- Bag
- Product Status:
- Obsolete
- Type:
- Fixed Point
- Interface:
- Host Interface, Serial Port
- Clock Rate:
- 20MHz
- Non-Volatile Memory:
- External
- On-Chip RAM:
- 10kB
- Voltage - I/O:
- 3.30V
- Voltage - Core:
- 3.30V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 128-TQFP (14x20)
ADSP-2173BST-80 FAQ
1.How can I place an order for ADSP-2173BST-80 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADSP-2173BST-80 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADSP-2173BST-80 reliable?
The price and inventory of ADSP-2173BST-80 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-2173BST-80 is usually 5 days.
3.What payment methods are accepted for ADSP-2173BST-80?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-2173BST-80 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADSP-2173BST-80?
ADSP-2173BST-80 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADSP-2173BST-80 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADSP-2173BST-80?
For technical support, including ADSP-2173BST-80 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-2173BST-80 requirements.
6.How does Aetrix verify that ADSP-2173BST-80 is sourced from the original manufacturer or authorized distributors?
All ADSP-2173BST-80 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-2173BST-80 meets industry standards.
7.What is the process for return or replacement of ADSP-2173BST-80?
All ADSP-2173BST-80 units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-2173BST-80, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADSP-2173BST-80 part is unused and in its original packaging.
Return procedure for ADSP-2173BST-80:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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