Analog Devices Inc. ADSP-21990BST
- Part No.:
- ADSP-21990BST
- Manufacturer:
- Analog Devices Inc.
- Category:
- DSP (Digital Signal Processors)
- Package:
- 176-LQFP
- Datasheet:
-
ADSP-21990BST.pdf
- Description:
- IC DSP CONTROLLER 16BIT 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADSP-21990BST from Analog Devices is a mixed-signal DSP controller featuring a 16-bit fixed-point ADSP-2199x core delivering 160 MIPS sustained performance at 160 MHz CCLK, 8K words on-chip RAM (4K×24-bit program + 4K×16-bit data), an 8-channel 14-bit ADC with 20 MSPS sampling, and a 3-phase 16-bit center-aligned PWM unit with 12.5 ns resolution-designed for industrial motor control systems requiring tight real-time signal processing and embedded analog/digital peripheral integration.
For engineers reviewing the ADSP-21990BST datasheet, ADSP-21990BST pinout, ADSP-21990BST application, or ADSP-21990BST equivalent, key selection considerations include its integrated ADC timing accuracy, PWM dead-time control capability, JTAG-emulation support, and compatibility with ADMCxxx legacy code in high-reliability motor drive designs.
Technical Context
The ADSP-21990BST implements a unified memory architecture with dual 24-bit PMA/DMA buses enabling simultaneous instruction fetch and dual-operand data access; its computational units-ALU, MAC (dual 40-bit accumulators), and barrel shifter-execute single-cycle instructions while supporting parallel memory transfers via dedicated DMA controller.
Its clock subsystem integrates a programmable PLL generating independent CCLK (up to 160 MHz) and HCLK (up to 80 MHz), and its peripheral set includes SPI/SPORT serial ports, three 32-bit interval timers, 16 flag I/O pins, watchdog timer, and encoder interface unit-all memory-mapped and interrupt-controlled via software-priority peripheral interrupt controller.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | 16-bit fixed-point ADSP-2199x DSP, code-compatible with ADSP-217xx/ADMCxxx, enabling legacy motor control firmware reuse. |
| Performance | 160 MIPS sustained at 160 MHz CCLK (6.25 ns instruction cycle), supporting real-time loop execution in servo drives. |
| On-Chip Memory | 4K × 24-bit program RAM + 4K × 16-bit data RAM - sufficient for compact control algorithms without external memory latency. |
| ADC System | 8-channel, 14-bit SAR ADC with dual-channel simultaneous sampling across 4 input pairs, 20 MSPS max rate at 160 MHz CCLK. |
| PWM Unit | 3-phase, 16-bit center-aligned PWM generator with 12.5 ns resolution and hardware dead-time insertion for IGBT gate driving. |
| Package | 196-ball CSP_BGA (12 mm × 12 mm, 0.8 mm pitch) - optimized for compact, thermally constrained motor control PCBs. |
| Operating Range | –40°C to +85°C ambient, 2.5 V core / 3.3 V I/O supply - suitable for industrial enclosure environments. |
Pinout & Package
The ADSP-21990BST is housed in a 196-ball CSP_BGA package with 0.8 mm ball pitch and 12 mm × 12 mm body size, designed for high-density routing and thermal dissipation in motor control modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CCLK | Core Clock Input | Accepts external clock or crystal; feeds PLL to generate internal 160 MHz CCLK for deterministic instruction timing. |
| HCLK | Peripheral Clock Output | Derived from CCLK (÷1 or ÷2); synchronizes ADC, PWM, SPI, and SPORT peripherals at up to 80 MHz. |
| AD0–AD7 | Analog Input Channels | Dedicated differential inputs for 8-channel 14-bit ADC; support simultaneous sampling on AD0/AD1, AD2/AD3, etc. |
| PWM0A–PWM3B | PWM Output Terminals | 6 dedicated outputs for 3-phase center-aligned PWM (A/B per phase); enable complementary gate drive with programmable dead time. |
| ENC_A, ENC_B, ENC_I | Encoder Interface Inputs | Quadrature A/B and index pulse inputs for high-resolution position feedback from incremental encoders. |
| PF0–PF15 | Programmable Flag I/O | 16 general-purpose digital I/O pins; PF0–PF7 configurable as SPI slave select outputs (SPISEL1–7) or GPIO. |
Key Features
| Feature | Design Value |
|---|---|
| Dedicated Memory DMA Controller | Enables zero-CPU-overhead data movement between internal RAM, external memory, and peripherals (ADC/SPI/SPORT), preserving real-time determinism. |
| Integrated 1.0 V Precision Voltage Reference | Stabilizes ADC full-scale range independently of external supply noise-critical for current sensing accuracy in motor phase measurement. |
| Software-Configurable Power Management | Supports idle and power-down modes with wake-on-interrupt; reduces active power to <50 mW during standby in UPS or portable instrumentation. |
| JTAG Emulation Support | IEEE 1149.1-compliant TAP enables real-time debugging, breakpoint injection, and register inspection without halting PWM or ADC operation. |
| Flexible Boot Options | Supports boot from internal ROM, external SPI EEPROM, or parallel flash-enabling field firmware updates and secure bootloader deployment. |
Applications
| Industrial Motor Drives | Uninterruptible Power Supplies (UPS) |
|---|---|
Use Scenario: Closed-loop field-oriented control (FOC) of 3-phase PMSM/BLDC motors in HVAC compressors and CNC spindles. IC Role / Device Role / Timing Role: Real-time DSP controller executing FOC algorithm, sampling current/voltage via integrated ADC, and generating synchronized PWM with nanosecond-level timing precision. Use Value: Eliminates need for external ADC, PWM generator, and encoder interface ICs-reducing BOM count and board area by >30% versus discrete solutions. | Use Scenario: Digital control of bidirectional AC/DC and DC/AC inverters in online double-conversion UPS systems. IC Role / Device Role / Timing Role: High-speed voltage/current regulation loop executor with 20 MSPS ADC sampling and 12.5 ns PWM resolution for harmonic suppression. Use Value: Enables adaptive dead-time compensation and fast overcurrent response (<2 µs detection-to-shutdown) improving system fault tolerance. |
| Optical Networking Control | Data Acquisition Systems |
Use Scenario: Laser diode bias and temperature control in DWDM transceivers requiring precise analog feedback loops. IC Role / Device Role / Timing Role: Mixed-signal controller managing DAC output, thermistor ADC readings, and PID computation with sub-microsecond loop latency. Use Value: On-chip 1.0 V reference and 14-bit ADC ensure ±0.1% full-scale linearity for laser power calibration traceability. | Use Scenario: Portable oscilloscope front-end capturing multi-channel analog waveforms at ≥10 MSPS with trigger and post-processing. IC Role / Device Role / Timing Role: Signal processor performing real-time FFT, filtering, and waveform reconstruction using on-chip 8K RAM buffer. Use Value: Dual-bus architecture allows concurrent ADC sampling and memory-to-DSP data transfer-achieving sustained 20 MSPS throughput without pipeline stalls. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar mixed-signal DSP controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TMS320F28335PTP | 32-bit C28x CPU, 150 MIPS, 256 KB Flash, no on-chip 14-bit ADC - relies on external ADC or lower-resolution internal 12-bit module. | Better suited for Flash-based standalone control where firmware update flexibility outweighs ADC precision requirements. | Select when prioritizing large program storage and C-language toolchain maturity over integrated high-fidelity analog acquisition. |
| ADSP-CM408FYSZ-4 | ARM Cortex-M4 core, 240 MHz, 384 KB SRAM, dual 16-bit 13 MSPS ADCs, but lacks dedicated PWM generation unit and encoder interface. | Ideal for sensor fusion and floating-point math-heavy applications where PWM is handled by external gate drivers or FPGA. | Choose when migrating toward ARM ecosystem and require floating-point acceleration, accepting added peripheral ICs for motor control. |
Compared with TMS320F28335PTP and ADSP-CM408FYSZ-4, the ADSP-21990BST delivers superior analog integration (14-bit ADC + 1.0 V ref) and hardware-accelerated motor control peripherals (3-phase PWM + EIU) in a single chip-making it optimal for cost-sensitive, space-constrained industrial drives where analog fidelity and deterministic timing are non-negotiable.
Availability
ADSP-21990BST is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, optical networking control, and portable instrumentation requiring stable component supply across extended production lifecycles.
Supply support for ADSP-21990BST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, headquartered in Norwood, MA, with design centers worldwide and a 50+ year heritage in precision signal processing.
The ADSP-2199x product line was engineered specifically for high-reliability industrial motor control, integrating deterministic DSP compute, high-resolution analog acquisition, and hardware-timed PWM/encoder interfaces into a single monolithic solution.
FAQ
What is the maximum ADC sampling rate supported by the ADSP-21990BST?
The ADSP-21990BST supports up to 20 MSPS sampling rate for its 8-channel, 14-bit ADC system when operating at the full 160 MHz CCLK. This rate is achievable with dual-channel simultaneous sampling across four input pairs (e.g., AD0/AD1, AD2/AD3), enabling precise current and voltage capture in three-phase motor control loops without external sample-and-hold circuitry. The ADSP-21990BST's internal 1.0 V reference ensures consistent full-scale accuracy across temperature.
Does the ADSP-21990BST support JTAG-based in-circuit debugging?
Yes, the ADSP-21990BST includes full IEEE JTAG Standard 1149.1 test access port support for on-chip emulation and real-time system debugging. Engineers can perform non-intrusive breakpoints, register inspection, and memory read/write operations while the ADSP-21990BST continues executing PWM generation and ADC sampling-ensuring deterministic behavior during development and validation of motor control firmware.
What package type is used for the ADSP-21990BST, and what are its key mechanical features?
The ADSP-21990BST uses a 196-ball CSP_BGA package measuring 12 mm × 12 mm with 0.8 mm ball pitch. Its compact footprint and low-profile construction support high-density PCB layouts in space-constrained motor drive modules. Thermal performance is enhanced by an exposed die pad compatible with standard reflow profiles, and the package is RoHS-compliant per Rev. A ordering guide.
How does the ADSP-21990BST handle power management in battery-powered instrumentation?
The ADSP-21990BST provides flexible power management with selectable idle and power-down modes, reducing active power consumption to under 50 mW during standby. Wake-on-interrupt capability allows rapid resumption of ADC sampling or PWM output within microseconds-ideal for portable data loggers or handheld test equipment where battery life and responsive wake-up are critical. The ADSP-21990BST maintains full peripheral functionality upon wake, including retained ADC calibration and PWM state.
Is the ADSP-21990BST pin-compatible with earlier ADSP-217xx-based ADMCxxx devices?
No, the ADSP-21990BST is not pin-compatible with ADSP-217xx-based ADMCxxx devices due to architectural expansion-including additional ADC channels, PWM outputs, and flag I/O pins-but it is code-compatible at the assembly level. Firmware written for ADMC301/331 can be recompiled for the ADSP-21990BST with minimal peripheral register mapping updates, preserving investment in motor control algorithms while gaining higher performance and integration.
ADSP-21990BST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- ADSP-21xx
- Package/Case:
- 176-LQFP
- Packaging:
- Bag
- Product Status:
- Obsolete
- Type:
- Fixed Point
- Interface:
- SPI, SSP
- Clock Rate:
- 160MHz
- Non-Volatile Memory:
- External
- On-Chip RAM:
- 20kB
- Voltage - I/O:
- 3.30V
- Voltage - Core:
- 2.50V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 176-LQFP (24x24)
ADSP-21990BST FAQ
1.How can I place an order for ADSP-21990BST through Aetrix?
Please submit a Request for Quotation (RFQ) for ADSP-21990BST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADSP-21990BST reliable?
The price and inventory of ADSP-21990BST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-21990BST is usually 5 days.
3.What payment methods are accepted for ADSP-21990BST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-21990BST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADSP-21990BST?
ADSP-21990BST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADSP-21990BST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADSP-21990BST?
For technical support, including ADSP-21990BST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-21990BST requirements.
6.How does Aetrix verify that ADSP-21990BST is sourced from the original manufacturer or authorized distributors?
All ADSP-21990BST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-21990BST meets industry standards.
7.What is the process for return or replacement of ADSP-21990BST?
All ADSP-21990BST units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-21990BST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADSP-21990BST part is unused and in its original packaging.
Return procedure for ADSP-21990BST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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