Analog Devices Inc. ADSP-21990BSTZ

Overview

ADSP-21990BSTZ from Analog Devices is a mixed-signal DSP controller featuring a 16-bit fixed-point ADSP-2199x core delivering 160 MIPS sustained performance at 160 MHz CCLK, integrated 4K × 24-bit program RAM and 4K × 16-bit data RAM, an 8-channel 14-bit ADC with 20 MSPS sampling rate, and a 3-phase 16-bit center-aligned PWM unit with 12.5 ns resolution - deployed in industrial motor drives and uninterruptible power supplies.

For engineers reviewing the ADSP-21990BSTZ datasheet, ADSP-21990BSTZ pinout, ADSP-21990BSTZ application, or ADSP-21990BSTZ equivalent, key selection criteria include on-chip memory partitioning (24-bit PM vs. 16-bit DM), dual-clock domain operation (CCLK up to 160 MHz / HCLK up to 80 MHz), ADC simultaneous sampling capability across four input pairs, and SPI/SPORT peripheral coexistence with DMA-controlled transfers.

Technical Context

The ADSP-21990BSTZ implements a unified memory architecture with two independent 24-bit address buses (PMA/DMA) and dual DAG units supporting circular buffering via 8-bit page registers (DMPG1/DMPG2) and modulo addressing within 64K-word pages. Its computational pipeline executes single-cycle instructions while concurrently handling instruction fetch, dual operand access, ALU/MAC/shifter operations, and peripheral I/O.

Peripherals operate in a dedicated clock domain (HCLK ≤ CCLK/2), with the ADC subsystem synchronized to CCLK for precise timing control of sample-and-hold; the PWM generation unit uses hardware-based center-aligned modulation with programmable dead-time insertion and fault protection inputs mapped to flag I/O pins.

Key Specifications

Pinout & Package

ADSP-21990BSTZ is housed in a 196-ball CSP_BGA package (ball pitch: 0.8 mm), thermally enhanced for high-density motor control PCB layouts. Pin functions are defined per Analog Devices Rev. A datasheet Section "Pin Function Descriptions" (pp. 16–18), with dedicated ball assignments for analog inputs (AD0–AD7), PWM outputs (PWM0A–PWM2B), encoder interface (QEA/QEB/QEI), SPI/SPORT signals, and 16 general-purpose flag I/O lines (PF0–PF15).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar mixed-signal DSP controller applications.

Compared with ADSP-21992BSTZ, the ADSP-21990BSTZ trades extended temperature rating and extra auxiliary PWM outputs for lower unit cost and identical core/peripheral functionality in standard industrial ambient conditions; versus TMS320F28335PGFA, it provides deterministic ROM boot, tighter ADC/PWM synchronization, and hardware encoder interface - reducing system-level component count and interrupt latency.

Availability

ADSP-21990BSTZ is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, data acquisition systems, and optical networking control requiring stable component supply across multi-year production cycles.

Supply support for ADSP-21990BSTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, industrial automation, and communications infrastructure.

The ADSP-2199x product line was designed specifically for real-time embedded control applications demanding tight integration of high-speed DSP computation with precision analog acquisition and deterministic PWM generation - targeting motor control, power conversion, and sensor-rich industrial systems.

FAQ

What is the maximum sampling rate supported by the ADC in ADSP-21990BSTZ?

The ADSP-21990BSTZ ADC supports up to 20 MSPS aggregate sampling rate when operating at the full 160 MHz core clock (CCLK). This rate is achieved through time-interleaved conversion across its eight 14-bit channels, with hardware support for simultaneous sampling across four differential input pairs - a capability directly leveraged in vector-controlled motor drives where phase current synchronization is critical. The ADC's internal precision 1.0 V reference ensures consistent linearity across the specified –40°C to +85°C operating range.

Does ADSP-21990BSTZ support booting from external memory?

Yes, ADSP-21990BSTZ supports multiple boot modes including parallel, serial (SPI), and host-boot configurations, all initiated from its on-chip 4K × 24-bit boot ROM located on Page 255. While the device always begins execution from this internal ROM, the boot loader can load application code from external memory via the EMI interface or SPI port - enabling flexible deployment in systems with limited on-chip memory or requiring field updates. No external boot PROM is required for basic operation.

How does the PWM generation unit in ADSP-21990BSTZ achieve 12.5 ns resolution?

The ADSP-21990BSTZ PWM generation unit achieves 12.5 ns resolution by deriving its timing base directly from the 160 MHz core clock (CCLK), resulting in an 8 ns fundamental period; hardware interpolation and counter prescaling extend effective resolution to 12.5 ns for fine-grained duty-cycle control. This resolution is maintained across all six PWM outputs (PWM0A/B through PWM2A/B) and supports center-aligned modulation with programmable dead-time insertion - essential for minimizing shoot-through risk in three-phase inverter bridges.

Can the SPI and SPORT peripherals operate simultaneously on ADSP-21990BSTZ?

Yes, the SPI and SPORT peripherals on ADSP-21990BSTZ operate independently and can be used concurrently without resource conflict. Each has dedicated DMA channels (SPI Rx/Tx and SPORT Rx/Tx) arbitrated separately per Table 1 in the datasheet, and both reside in distinct I/O memory pages (Page 0 for SPI, Page 1 for SPORT). This allows simultaneous communication with an external EEPROM via SPI while streaming real-time sensor data over SPORT to an FPGA - a common architecture in modular industrial controllers where protocol isolation and bandwidth segregation are required.

What is the function of the DMPG1 and DMPG2 registers in ADSP-21990BSTZ memory addressing?

The DMPG1 and DMPG2 registers in ADSP-21990BSTZ hold the upper 8 bits of 24-bit memory addresses generated by Data Address Generators 1 and 2, respectively. Since each DAG's index register is only 16 bits wide, DMPG1/DMPG2 supply the most significant byte needed to access the full 16M-word address space across 256 pages. DMPG1 is also used during external memory accesses, requiring explicit programming before referencing off-chip variables - a requirement enforced by the compiler's "set_dmpg1()" macro to ensure correct page alignment in C code.