Analog Devices Inc. ADSP-21991BSTZ

Overview

ADSP-21991BSTZ from Analog Devices is a mixed-signal digital signal processor controller integrating a 16-bit fixed-point ADSP-219x core (160 MIPS), 40K words on-chip RAM (32K×24-bit PM + 8K×16-bit DM), 8-channel 14-bit ADC (20 MSPS), three-phase 16-bit center-aligned PWM (12.5 ns resolution), and encoder interface - deployed in industrial motor drives and uninterruptible power supplies.

For engineers reviewing the ADSP-21991BSTZ datasheet, ADSP-21991BSTZ pinout, ADSP-21991BSTZ application, or ADSP-21991BSTZ equivalent, key selection criteria include sustained 160 MIPS performance at 2.5 V core/3.3 V I/O, integrated analog-to-digital conversion with simultaneous dual-channel sampling, deterministic PWM timing for field-oriented control, and JTAG-compliant on-chip emulation support.

Technical Context

The ADSP-21991BSTZ implements a pipelined 16-bit fixed-point DSP core with dual DAGs, independent ALU/MAC/shifter units, and dual 40-bit accumulators - enabling parallel instruction fetch, dual operand access, and single-cycle computation. Its memory architecture unifies 24-bit program and 16-bit data address spaces across on-chip SRAM and configurable external banks.

Peripherals are tightly coupled via dedicated DMA channels: ADC, SPORT, and SPI each have autonomous DMA descriptors; the PWM generation unit operates synchronously with the 160 MHz CCLK and supports dead-time insertion; the encoder interface unit provides quadrature decoding with event-timer timestamping - all managed by a software-priority interrupt controller supporting 12 user-defined peripheral interrupts.

Key Specifications

Pinout & Package

The ADSP-21991BSTZ is housed in a 196-ball Mini-BGA package (12 mm × 12 mm, 1.0 mm ball pitch) with perimeter I/O arrangement optimized for high-density motor control PCB layouts. Ball assignment follows JEDEC MO-251 standard with dedicated power/ground planes and controlled-impedance routing zones for ADC and PWM signals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar mixed-signal DSP controller applications.

Compared with ADSP-21991BSTZ, ADSP-21992BSTZ offers identical real-time control capability with boot-mode variation only, whereas TMS320F28335PGFA trades ADC resolution and deterministic PWM timing for larger embedded Flash and C28x instruction set compatibility - making ADSP-21991BSTZ optimal for latency-critical, high-fidelity analog acquisition in motor and power conversion.

Availability

ADSP-21991BSTZ is available at Aetrix Electronics and suitable for industrial motor drives, uninterruptible power supplies, and optical networking control requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized channels.

Supply support for ADSP-21991BSTZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, founded in 1965 and headquartered in Wilmington, MA.

The ADSP-219x product line delivers integrated mixed-signal DSP controllers optimized for real-time industrial motion control, combining deterministic processing, precision analog interfaces, and motor-specific peripherals in a single chip.

FAQ

What is the maximum sustained processing performance of the ADSP-21991BSTZ?

The ADSP-21991BSTZ delivers 160 MIPS sustained performance at 160 MHz core clock (CCLK) with a 6.25 ns instruction cycle time. All instructions - except two multiword types - execute in a single cycle. This performance level is maintained under full load with concurrent ADC sampling, PWM generation, and DMA transfers, as verified in Analog Devices' ADSP-21991 datasheet Rev. 0 timing specifications.

Does the ADSP-21991BSTZ include an integrated voltage reference for its ADC?

Yes, the ADSP-21991BSTZ integrates a precision 1.0 V voltage reference (±1.5% over −40°C to +85°C) that directly supplies the 8-channel 14-bit ADC subsystem. This eliminates the need for an external reference component, reduces board area, and improves measurement stability by removing trace impedance and noise coupling variables - a key design value confirmed in the Functional Block Diagram and General Description sections of the ADSP-21991 datasheet.

How many PWM output channels does the ADSP-21991BSTZ support, and what is their timing resolution?

The ADSP-21991BSTZ supports six primary PWM outputs (three complementary phase pairs) plus two auxiliary PWM outputs. Its three-phase 16-bit center-aligned PWM generation unit achieves 12.5 ns resolution at 160 MHz CCLK - enabling sub-microsecond dead-time control and precise duty-cycle modulation critical for IGBT/MOSFET gate drivers in motor inverters, as specified in the KEY FEATURES section of the ADSP-21991 datasheet.

What package type and ball count does the ADSP-21991BSTZ use?

The ADSP-21991BSTZ uses a 196-ball Mini-BGA package (suffix BSTZ), measuring 12 mm × 12 mm with 1.0 mm ball pitch and compliant with JEDEC MO-251. This package is distinct from the 176-lead LQFP variant (ADSP-21991BSWZ) and is optimized for thermal dissipation and high-density routing in motor control PCBs - details confirmed in the Pin Configurations and Outline Dimensions sections of the ADSP-21991 datasheet Rev. 0.

Can the ADSP-21991BSTZ boot from external memory, and what interfaces support this?

Yes, the ADSP-21991BSTZ supports four boot modes: internal ROM, external SPI flash, external memory via EMI, or host loader via SPORT. Booting from external SPI flash is enabled by configuring the BMODE pins and leveraging the integrated SPI port in master mode - a capability documented in the Booting Modes section (Page 13) and SPI Port description of the ADSP-21991 datasheet, ensuring flexible firmware deployment and field updates without requiring JTAG intervention.