Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Embedded > DSP (Digital Signal Processors)

Analog Devices Inc. ADSP-SC584BBCZ-3A

Name: ADSP-SC584BBCZ-3A
Brand: Analog Devices Inc.
SKU: ADSP-SC584BBCZ-3A
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ADSP-SC584BBCZ-3A

Manufacturer:: Analog Devices Inc.

Category:: DSP (Digital Signal Processors)

Package:: 349-LFBGA, CSPBGA

Datasheet:: ADSP-SC584BBCZ-3A.pdf

Description:: ARM, 2XSHARC, DDR, LPC PACKAGE

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,264

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ADSP-SC584BBCZ-3A from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor, delivering 500 MHz per SHARC+ core and 500 MHz Arm Cortex-A5 operation. It features 5 Mb L1 SRAM per SHARC+ core (with parity), 256 kB L2 cache with parity, and supports 32-/40-/64-bit floating-point arithmetic. Designed for automotive audio processing, it integrates dual CAN 2.0 interfaces, 8-channel 12-bit HADC, and AEC-Q100 qualification.

For engineers reviewing the ADSP-SC584BBCZ-3A datasheet, ADSP-SC584BBCZ-3A pinout, ADSP-SC584BBCZ-3A application, or ADSP-SC584BBCZ-3A equivalent, key selection considerations include dual-core SHARC+ clock speed, L1 SRAM configuration options, Arm TrustZone security support, PCIe 2.0 lane availability, and 349-ball 0.8 mm pitch BGA package compatibility.

Technical Context

The ADSP-SC584BBCZ-3A implements a heterogeneous dual-architecture system: two SHARC+ SIMD cores operate at up to 500 MHz with independent 5 Mb L1 SRAM banks (configurable as SRAM or cache), while the Arm Cortex-A5 runs at 500 MHz with 32 kB I-cache/32 kB D-cache and 256 kB L2 cache with parity. The cores share a coherent system fabric via PL310 L2 cache controller and GIC-390 interrupt controller.

It integrates dedicated hardware accelerators including pipelined FFT/IFFT, FIR/IIR, harmonic analysis engine (HAE), SINC filter, and cryptographic engines supporting fast secure boot and Arm TrustZone. Memory subsystem includes 256 kB ECC-protected L2 SRAM, 512 kB L2 ROM, and dual 16-bit L3 interfaces supporting DDR3L, DDR2, and LPDDR1.

Key Specifications

Parameter	Value and Actual Design Meaning
SHARC+ Core Frequency	500 MHz - Enables real-time execution of high-throughput audio algorithms such as multi-band parametric EQ and active noise cancellation on each core.
Arm Cortex-A5 Frequency	500 MHz - Supports Linux-based middleware, network stack handling, and UI management without compromising DSP latency.
L1 SRAM per SHARC+ Core	5 Mb (640 kB) with parity - Provides single-cycle access for time-critical signal processing kernels; parity enables error detection in safety-critical automotive use.
L2 Cache	256 kB with parity - Shared between Arm and SHARC+ cores; ensures cache coherency for mixed-mode applications like voice assistant + audio rendering.
Package	349-ball CSP_BGA, 19 mm × 19 mm, 0.8 mm pitch - RoHS-compliant footprint compatible with standard automotive PCB assembly processes.
Automotive Qualification	AEC-Q100 Grade 2 (−40°C to +105°C) - Validated for under-hood and infotainment module deployment in passenger vehicles.
Integrated Peripherals	Dual CAN 2.0, 3× I²C, 2× SPI + 1× Quad-SPI, 3× UARTs, 2× USB 2.0 HS, 2× EMAC, PCIe 2.0 (1 lane), 8× timers - Enables direct connectivity to vehicle networks, sensors, displays, and storage without external bridge ICs.

Pinout & Package

ADSP-SC584BBCZ-3A uses a 349-ball CSP_BGA package (19 mm × 19 mm, 0.8 mm pitch), RoHS compliant. Ball assignments are defined in Analog Devices' ADSP-SC58x Designer Quick Reference (Rev. C, pp. 158–162) and support multiplexed GPIO, DAI, and peripheral functions across Ports A–E.

Pin/Terminal	Circuit Role	Design Meaning
CLKIN	Reference Clock Input	Accepts 1–50 MHz crystal or LVCMOS clock; feeds CGU for internal PLL generation of core/system clocks.
VDDIO_1P8 / VDDIO_3P3	I/O Power Supply	Separate 1.8 V and 3.3 V domains enable mixed-voltage interface support (e.g., 1.8 V SDIO, 3.3 V CAN transceivers).
BOOT_CFG[3:0]	Boot Configuration Pins	Strapped at power-up to select boot source: SPI flash, parallel NOR/NAND, or USB recovery mode.
RESET_OUT	System Reset Output	Drives reset to companion devices (e.g., audio codecs, PMICs); synchronized to internal reset controller timing.
TRST_N	JTAG Test Reset	Active-low asynchronous reset for JTAG TAP controller; required for boundary scan and debug initialization.

Key Features

Feature	Design Value
Dual SHARC+ + Arm Cortex-A5 Heterogeneous Architecture	Enables concurrent real-time DSP (e.g., beamforming, echo cancellation) and application-layer tasks (e.g., Bluetooth stack, GUI) on a single die-reducing BOM count and inter-chip latency.
Hardware Acceleration Engines (FFT/IFFT, FIR, IIR, HAE, SINC)	Offloads >90% of compute-intensive filtering and spectral analysis from CPU cores, freeing SHARC+ cycles for custom algorithm development.
Arm TrustZone + Cryptographic Hardware Accelerators	Supports secure boot, encrypted firmware updates, and isolated secure world execution-meeting ISO 21434 and AUTOSAR SecOC requirements.
Integrated 8-Channel 12-Bit HADC with ASRC	Direct analog input acquisition for microphones/sensors; ASRC enables sample rate conversion between asynchronous domains (e.g., 44.1 kHz mic → 48 kHz DSP pipeline).
Dual CAN 2.0 + PCIe 2.0 (1 Lane) + Dual EMAC	Provides native connectivity to vehicle CAN bus, high-speed diagnostics (PCIE), and Ethernet AVB for time-synchronized audio streaming in automotive cockpit systems.

Applications

Automotive Infotainment Head Unit	Professional Audio Digital Mixer
Use Scenario: Central audio processing unit in a vehicle head unit managing voice assistant, navigation prompts, media playback, and surround sound rendering. IC Role / Device Role / Timing Role: Primary SoC executing Linux on Arm Cortex-A5 for UI/networking and real-time audio algorithms on dual SHARC+ cores with sub-50 µs latency. Use Value: Eliminates need for discrete DSP + application processor combo; PCIe enables direct connection to display controller, while dual CAN interfaces integrate with vehicle bus for status reporting.	Use Scenario: 32-channel digital mixing console performing real-time dynamics processing, reverb, and effects routing for live sound reinforcement. IC Role / Device Role / Timing Role: Core audio processing engine handling 96 kHz/24-bit streams across multiple DAI interfaces with deterministic low-jitter clock generation. Use Value: Full SPORT and S/PDIF support enables daisy-chained I/O expansion; 5 Mb L1 SRAM per core stores large FIR coefficients for linear-phase EQ without external memory access.
Advanced Driver Assistance System (ADAS) Audio Preprocessor	Industrial Vibration Analysis Edge Node
Use Scenario: In-cabin microphone array preprocessing for occupant detection, speech command isolation, and acoustic event classification (e.g., glass break, horn). IC Role / Device Role / Timing Role: Real-time sensor fusion hub combining 8-channel HADC inputs with IMU data over SPI, running beamforming and neural inference kernels on SHARC+. Use Value: On-chip cryptographic acceleration secures OTA updates; AEC-Q100 qualification ensures reliability in temperature-cycled cabin environments.	Use Scenario: Standalone vibration monitoring node attached to rotating machinery, performing spectral analysis and anomaly detection at edge. IC Role / Device Role / Timing Role: Autonomous data acquisition and FFT-based feature extraction engine using HADC and hardware-accelerated FFT/IFFT engines. Use Value: 256 kB L2 SRAM stores time-series buffers; dual timer units trigger synchronized sampling; low-power modes extend battery life in wireless deployments.

Automotive Infotainment Head Unit

Professional Audio Digital Mixer

Use Scenario: Central audio processing unit in a vehicle head unit managing voice assistant, navigation prompts, media playback, and surround sound rendering.

IC Role / Device Role / Timing Role: Primary SoC executing Linux on Arm Cortex-A5 for UI/networking and real-time audio algorithms on dual SHARC+ cores with sub-50 µs latency.

Use Value: Eliminates need for discrete DSP + application processor combo; PCIe enables direct connection to display controller, while dual CAN interfaces integrate with vehicle bus for status reporting.

Use Scenario: 32-channel digital mixing console performing real-time dynamics processing, reverb, and effects routing for live sound reinforcement.

IC Role / Device Role / Timing Role: Core audio processing engine handling 96 kHz/24-bit streams across multiple DAI interfaces with deterministic low-jitter clock generation.

Use Value: Full SPORT and S/PDIF support enables daisy-chained I/O expansion; 5 Mb L1 SRAM per core stores large FIR coefficients for linear-phase EQ without external memory access.

Advanced Driver Assistance System (ADAS) Audio Preprocessor

Industrial Vibration Analysis Edge Node

Use Scenario: In-cabin microphone array preprocessing for occupant detection, speech command isolation, and acoustic event classification (e.g., glass break, horn).

IC Role / Device Role / Timing Role: Real-time sensor fusion hub combining 8-channel HADC inputs with IMU data over SPI, running beamforming and neural inference kernels on SHARC+.

Use Value: On-chip cryptographic acceleration secures OTA updates; AEC-Q100 qualification ensures reliability in temperature-cycled cabin environments.

Use Scenario: Standalone vibration monitoring node attached to rotating machinery, performing spectral analysis and anomaly detection at edge.

IC Role / Device Role / Timing Role: Autonomous data acquisition and FFT-based feature extraction engine using HADC and hardware-accelerated FFT/IFFT engines.

Use Value: 256 kB L2 SRAM stores time-series buffers; dual timer units trigger synchronized sampling; low-power modes extend battery life in wireless deployments.

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP + application processor applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADSP-SC587BBCZ-5A	529-ball BGA, dual 16-bit L3 memory controllers, 10/100/1000 EMAC + IEEE 1588, SDIO/eMMC support	Targeted at higher-bandwidth systems requiring Gigabit Ethernet AVB, expanded memory bandwidth, and embedded storage	Select when needing PCIe + Gigabit EMAC + SDIO in same package; not pin-compatible due to larger ball count and different peripheral mapping.
ADSP-SC584WBCZ-3A	AEC-Q100 Grade 1 (−40°C to +125°C), identical core/peripheral spec but qualified for extended automotive temperature range	Required for engine bay or transmission control module integration where ambient exceeds +105°C	Choose for under-hood deployment; shares same 349-ball footprint and software compatibility but requires automotive-grade validation documentation.

Compared with ADSP-SC584BBCZ-3A, the ADSP-SC587BBCZ-5A adds memory bandwidth and networking capability at the cost of larger package and layout redesign, while ADSP-SC584WBCZ-3A extends thermal range without functional change-making it a drop-in replacement only for higher-temperature mechanical environments.

Availability

ADSP-SC584BBCZ-3A is available at Aetrix Electronics and suitable for automotive infotainment, professional audio equipment, and industrial edge analytics requiring stable component supply, long lifecycle support, and AEC-Q100 compliance.

Supply support for ADSP-SC584BBCZ-3A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision, power, and connectivity applications.

The ADSP-SC584BBCZ-3A belongs to the SHARC+ family-a line of heterogeneous processors designed specifically for real-time audio, motor control, and safety-critical embedded systems demanding both floating-point DSP performance and application-level programmability.

FAQ

What is the maximum operating frequency of each SHARC+ core in the ADSP-SC584BBCZ-3A?

The ADSP-SC584BBCZ-3A supports up to 500 MHz per SHARC+ core, as confirmed in Table 2 of the Rev. C datasheet. This frequency is achievable under specified voltage (1.1 V core) and temperature (−40°C to +105°C) conditions, enabling sustained 4000 MFLOPS peak performance per core for floating-point intensive workloads.

Does the ADSP-SC584BBCZ-3A include hardware support for secure boot and firmware encryption?

Yes, the ADSP-SC584BBCZ-3A integrates cryptographic hardware accelerators and supports fast secure boot with IP protection, as stated in the "Additional Features" section. It also implements Arm TrustZone to isolate secure world execution, allowing encrypted firmware images to be authenticated and decrypted in hardware before loading into L2 ROM or L1 SRAM.

Is the ADSP-SC584BBCZ-3A pin-compatible with other members of the ADSP-SC58x family?

No-pin compatibility is limited to same-package variants. The ADSP-SC584BBCZ-3A uses the 349-ball CSP_BGA package, matching ADSP-SC582/SC583/SC584/21583/21584 in ball count and pitch, but differences in peripheral enablement (e.g., PCIe presence only in SC584/SC587/SC589) mean pin functions are not fully interchangeable without reviewing GPIO multiplexing tables and signal descriptions in the datasheet.

What types of floating-point formats does the ADSP-SC584BBCZ-3A support?

The ADSP-SC584BBCZ-3A supports 32-bit IEEE single-precision, 40-bit extended-precision, and 64-bit IEEE double-precision floating-point arithmetic natively in its SHARC+ cores. It also supports 16-bit floating-point storage format, which doubles on-chip data capacity and is convertible to/from 32-bit format in a single instruction.

Can the Arm Cortex-A5 core in the ADSP-SC584BBCZ-3A run a full Linux distribution?

Yes-the ADSP-SC584BBCZ-3A's 500 MHz Arm Cortex-A5 with 32 kB I-cache, 32 kB D-cache, and 256 kB L2 cache meets minimum requirements for lightweight Linux distributions (e.g., Yocto Project BSP). Analog Devices provides official Linux kernel support, device tree bindings, and root filesystem examples targeting this exact part number.

ADSP-SC584BBCZ-3A Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: SHARC®

Package/Case:: 349-LFBGA, CSPBGA

Packaging:: Tray

Product Status:: Active

Type:: Floating Point

Interface:: CAN, EBI/EMI, Ethernet, DAI, I2C, MMC/SD/SDIO, SPI, SPORT, UART/USART, USB OTG

Clock Rate:: 300MHz

Non-Volatile Memory:: ROM (512kB)

On-Chip RAM:: 640kB

Voltage - I/O:: 3.30V

Voltage - Core:: 1.10V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 349-CSPBGA (19x19)

ADSP-SC584BBCZ-3A FAQ

1.How can I place an order for ADSP-SC584BBCZ-3A through Aetrix?

Please submit a Request for Quotation (RFQ) for ADSP-SC584BBCZ-3A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADSP-SC584BBCZ-3A reliable?

The price and inventory of ADSP-SC584BBCZ-3A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-SC584BBCZ-3A is usually 5 days.

3.What payment methods are accepted for ADSP-SC584BBCZ-3A?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-SC584BBCZ-3A transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADSP-SC584BBCZ-3A?

ADSP-SC584BBCZ-3A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADSP-SC584BBCZ-3A order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADSP-SC584BBCZ-3A?

For technical support, including ADSP-SC584BBCZ-3A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-SC584BBCZ-3A requirements.

6.How does Aetrix verify that ADSP-SC584BBCZ-3A is sourced from the original manufacturer or authorized distributors?

All ADSP-SC584BBCZ-3A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-SC584BBCZ-3A meets industry standards.

7.What is the process for return or replacement of ADSP-SC584BBCZ-3A?

All ADSP-SC584BBCZ-3A units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-SC584BBCZ-3A, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADSP-SC584BBCZ-3A part is unused and in its original packaging.

Return procedure for ADSP-SC584BBCZ-3A:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…