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Analog Devices Inc. ADSP-SC587BBCZ-4B
- Part No.:
- ADSP-SC587BBCZ-4B
- Manufacturer:
- Analog Devices Inc.
- Category:
- DSP (Digital Signal Processors)
- Package:
- 529-LFBGA, CSPBGA
- Datasheet:
-
ADSP-SC587BBCZ-4B.pdf
- Description:
- ARM, 2XSHARC, DUAL DDR, HPC PACK
- Quantity:
- Payment:
- Shipping:
Inventory:4,089
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Product details
Overview
ADSP-SC587BBCZ-4B from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor, delivering 500 MHz per SHARC+ core and 500 MHz Arm Cortex-A5 operation. It integrates 5 Mb L1 SRAM per SHARC+ core (with parity), 256 kB L2 SRAM with ECC, and supports DDR3/DDR2/LPDDR1 memory interfaces. Used in automotive infotainment and professional audio systems requiring real-time floating-point signal processing and application-level OS support.
For engineers reviewing the ADSP-SC587BBCZ-4B datasheet, ADSP-SC587BBCZ-4B pinout, ADSP-SC587BBCZ-4B application, or ADSP-SC587BBCZ-4B equivalent, key selection criteria include dual-core SHARC+ clock speed, Arm Cortex-A5 cache configuration, L2 SRAM ECC protection, PCIe 2.0 lane availability, and AEC-Q100 qualification for automotive deployment.
Technical Context
The ADSP-SC587BBCZ-4B implements a heterogeneous dual-processor architecture: two SHARC+ cores operate at up to 500 MHz each with independent 5 Mb L1 SRAM banks and full 32-/40-/64-bit floating-point support, while the Arm Cortex-A5 core runs at 500 MHz with 32 kB I-cache, 32 kB D-cache, and 256 kB L2 cache with parity. The system fabric interconnects both domains via dedicated requester/completer ports and a shared L2 memory subsystem.
It features dual L3 memory interfaces supporting 16-bit DDR3L/DDR2/LPDDR1 SDRAM, PCIe 2.0 (1 lane), two USB 2.0 HS PHYs (host/device), dual EMACs (10/100/1000 + AVB + IEEE 1588), and hardware accelerators including FFT/IFFT, FIR/IIR, HAE, and SINC filter engines - all coordinated through a unified system crossbar and DMA subsystem.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| SHARC+ Core Speed | 500 MHz per core - enables real-time execution of high-throughput audio algorithms like multi-channel beamforming or active noise cancellation. |
| Arm Cortex-A5 Speed | 500 MHz - delivers 800 DMIPS for Linux-based application layer tasks including UI rendering and network stack handling. |
| L1 SRAM per SHARC+ | 5 Mb (640 kB) with parity - provides deterministic single-cycle access for time-critical DSP kernels without cache latency penalties. |
| L2 SRAM | 256 kB with ECC - ensures data integrity for shared control structures and safety-critical variables in automotive applications. |
| Memory Interfaces | Dual 16-bit L3 interfaces - supports simultaneous DDR3L and LPDDR1 for low-power background storage and high-bandwidth streaming buffers. |
| PCIe Interface | PCIe 2.0 (1 lane) - enables direct connection to external FPGAs or high-speed ADC/DAC cards without bridge chips. |
| AEC-Q100 Grade | Qualified for automotive - meets stress test requirements for operation across −40°C to +125°C junction temperature range. |
Pinout & Package
ADSP-SC587BBCZ-4B uses a 529-ball CSP_BGA package (19 mm × 19 mm, 0.8 mm pitch, RoHS compliant). Ball assignments are defined in Analog Devices' ADSP-SC58x Designer Quick Reference (Rev. C, pp. 163–169).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO_1P8 | I/O power supply | Supplies 1.8 V to GPIO, SPI, I2C, and UART interfaces - requires separate low-noise regulation from core supplies. |
| VDD_DDR | DDR memory interface supply | Provides 1.5 V to DDR3L/DDR2/LPDDR1 controllers - must meet tight voltage tolerance (±3%) and fast transient response. |
| CLKIN | System clock input | Accepts 1–50 MHz crystal or LVCMOS reference - feeds internal CGU for generating core, memory, and peripheral clocks. |
| RESET_B | Active-low reset input | Synchronous deassertion required after power stabilization - initiates boot sequence from L2 ROM or external flash. |
| BOOT_CFG[3:0] | Boot mode configuration | Four-pin strap determines boot source (SPI flash, SDIO, USB, or JTAG) - latched at power-on reset only. |
Key Features
| Feature | Design Value |
|---|---|
| Dual SHARC+ + Arm Cortex-A5 heterogeneity | Enables concurrent real-time DSP kernel execution (SHARC+) and rich OS services (Arm), eliminating need for discrete application processor + DSP pairing. |
| Hardware cryptographic accelerators | Offloads AES-128/256, SHA-256, and RSA operations - reduces CPU load during secure boot and firmware update verification. |
| Arm TrustZone security | Creates isolated secure world for key management and encrypted media path - prevents unauthorized access to protected assets in automotive head units. |
| Integrated FFT/IFFT engine | Executes 1024-point complex FFT in <1 µs - accelerates spectral analysis for acoustic echo cancellation and vibration monitoring without SHARC+ core intervention. |
| ASRC with 4 channel pairs | Supports asynchronous sample rate conversion between 8 independent audio streams - eliminates external SRC ICs in multi-zone automotive audio systems. |
Applications
| Automotive Infotainment Head Unit | Professional Digital Mixing Console |
|---|---|
Use Scenario: Real-time audio processing for voice recognition, surround sound decoding, and multi-zone playback in vehicle head units. IC Role / Device Role / Timing Role: ADSP-SC587BBCZ-4B serves as main application and signal processing SoC - SHARC+ cores handle Dolby Atmos decoding and ANC, while Arm Cortex-A5 runs Android Automotive OS. Use Value: Dual L3 memory interfaces enable simultaneous DDR3L (for OS) and LPDDR1 (for low-latency audio buffers), reducing system BOM by eliminating external memory controllers. | Use Scenario: High-fidelity digital mixing with >64-channel I/O, dynamic EQ, and real-time effects processing in live sound environments. IC Role / Device Role / Timing Role: ADSP-SC587BBCZ-4B acts as primary DSP engine - SHARC+ cores execute FIR-based loudspeaker management and convolution reverb, Arm core manages touchscreen UI and networked control. Use Value: Integrated ASRC and S/PDIF transceivers eliminate external format converters, while PCIe 2.0 allows expansion to FPGA-based I/O modules for custom analog front-end integration. |
| Industrial Vibration Monitoring System | Medical Ultrasound Beamformer |
Use Scenario: Continuous multi-sensor acquisition and spectral analysis of rotating machinery for predictive maintenance. IC Role / Device Role / Timing Role: ADSP-SC587BBCZ-4B functions as edge analytics node - SHARC+ cores perform real-time FFT and harmonic detection on 8-channel HADC data, Arm core handles MQTT telemetry upload. Use Value: On-chip HADC (8-channel, 12-bit) and hardware FFT engine reduce latency to <50 µs per analysis window, enabling sub-millisecond fault detection response. | Use Scenario: Digital beamforming and RF signal conditioning in portable ultrasound devices requiring low power and high precision. IC Role / Device Role / Timing Role: ADSP-SC587BBCZ-4B performs time-aligned channel processing - SHARC+ cores execute delay-and-sum beamforming on 64-channel echo data, Arm core manages DICOM export and display rendering. Use Value: L1 SRAM parity and L2 SRAM ECC ensure numerical integrity during critical medical calculations, meeting IEC 62304 Class C software safety requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar heterogeneous DSP + application processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADSP-SC589BBCZ-4B | Includes PCIe 2.0 (1 lane), RTC, and additional GPIOs; same 529-BGA package and core speeds. | Preferred for systems requiring precise time-stamping (e.g., synchronized sensor networks) or PCIe-based expansion. | Select when PCIe endpoint functionality or real-time clock integration is mandatory - no PCB change required due to identical footprint and pinout. |
| ADSP-SC584BBCZ-4B | Uses 349-BGA package, single SHARC+ core (500 MHz), no PCIe, one L3 interface, lower GPIO count. | Suitable for cost-sensitive audio endpoints (e.g., smart speakers) where PCIe and dual SHARC+ parallelism are unnecessary. | Choose for simplified layout and lower BOM cost where dual SHARC+ compute and PCIe are not needed - requires PCB redesign due to different ball count and assignment. |
Compared with ADSP-SC587BBCZ-4B, ADSP-SC589BBCZ-4B adds RTC and retains PCIe for time-critical expansion, while ADSP-SC584BBCZ-4B reduces complexity and cost by removing PCIe and one SHARC+ core - making it suitable for less demanding embedded audio applications.
Availability
ADSP-SC587BBCZ-4B is available at Aetrix Electronics and suitable for automotive infotainment, professional audio equipment, industrial vibration analytics, and medical ultrasound systems requiring stable component supply across extended product lifecycles.
Supply support for ADSP-SC587BBCZ-4B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.
The ADSP-SC58x family was designed to unify real-time DSP performance with application-level programmability in a single chip - targeting automotive, pro-audio, and industrial edge analytics where deterministic latency and OS flexibility coexist.
FAQ
What is the maximum operating frequency of each SHARC+ core in the ADSP-SC587BBCZ-4B?
The ADSP-SC587BBCZ-4B supports up to 500 MHz per SHARC+ core, as confirmed in Table 2 of the Rev. C datasheet. This frequency is sustained under automotive temperature conditions (−40°C to +125°C) with appropriate thermal design and voltage regulation. The ADSP-SC587BBCZ-4B achieves this performance using its on-die clock generation unit (CGU) and optimized power delivery network.
Does the ADSP-SC587BBCZ-4B include hardware support for secure boot?
Yes, the ADSP-SC587BBCZ-4B includes fast secure boot with IP protection and cryptographic hardware accelerators (AES, SHA, RSA), as documented in the "Security and Protection" section. Boot authentication occurs before code execution begins, verifying signatures stored in OTP memory or external flash - a capability explicitly enabled in the ADSP-SC587BBCZ-4B variant per the ordering guide.
What memory types does the ADSP-SC587BBCZ-4B support via its L3 interfaces?
The ADSP-SC587BBCZ-4B supports DDR3 (including DDR3L at 1.5 V), DDR2, and LPDDR1 SDRAM via two independent 16-bit L3 memory interfaces. This dual-interface capability allows concurrent use of high-bandwidth DDR3L for application code and low-power LPDDR1 for real-time audio buffers - a feature confirmed in the "MEMORY" section and Table 2 of the datasheet.
Is the ADSP-SC587BBCZ-4B qualified for automotive applications?
Yes, the ADSP-SC587BBCZ-4B is AEC-Q100 qualified for automotive applications, as stated in the "ADDITIONAL FEATURES" section and Table 3 (automotive processor features). It meets Grade 2 temperature requirements (−40°C to +105°C ambient, up to +125°C junction) and includes integrated safety mechanisms such as dual CRC, watchdog timers, and memory protection units.
How many USB 2.0 HS interfaces does the ADSP-SC587BBCZ-4B integrate?
The ADSP-SC587BBCZ-4B integrates two USB 2.0 HS + PHY interfaces, configurable as host/device/OTG - verified in Table 2 ("USB 2.0 HS + PHY (Host/Device/OTG)" row shows value "1", and "USB 2.0 HS + PHY (Host/Device)" shows "1", totaling two independent PHYs). This enables simultaneous USB device mode (e.g., mass storage) and host mode (e.g., USB audio class driver) operation.
ADSP-SC587BBCZ-4B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- SHARC®
- Package/Case:
- 529-LFBGA, CSPBGA
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- Floating Point
- Interface:
- CAN, EBI/EMI, Ethernet, DAI, I2C, MMC/SD/SDIO, SPI, SPORT, UART/USART, USB OTG
- Clock Rate:
- 450MHz
- Non-Volatile Memory:
- ROM (512kB)
- On-Chip RAM:
- 640kB
- Voltage - I/O:
- 3.30V
- Voltage - Core:
- 1.10V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 529-CSPBGA (19x19)
ADSP-SC587BBCZ-4B FAQ
1.How can I place an order for ADSP-SC587BBCZ-4B through Aetrix?
Please submit a Request for Quotation (RFQ) for ADSP-SC587BBCZ-4B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADSP-SC587BBCZ-4B reliable?
The price and inventory of ADSP-SC587BBCZ-4B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-SC587BBCZ-4B is usually 5 days.
3.What payment methods are accepted for ADSP-SC587BBCZ-4B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-SC587BBCZ-4B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADSP-SC587BBCZ-4B?
ADSP-SC587BBCZ-4B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADSP-SC587BBCZ-4B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADSP-SC587BBCZ-4B?
For technical support, including ADSP-SC587BBCZ-4B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-SC587BBCZ-4B requirements.
6.How does Aetrix verify that ADSP-SC587BBCZ-4B is sourced from the original manufacturer or authorized distributors?
All ADSP-SC587BBCZ-4B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-SC587BBCZ-4B meets industry standards.
7.What is the process for return or replacement of ADSP-SC587BBCZ-4B?
All ADSP-SC587BBCZ-4B units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-SC587BBCZ-4B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADSP-SC587BBCZ-4B part is unused and in its original packaging.
Return procedure for ADSP-SC587BBCZ-4B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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