Analog Devices Inc. ADSP-SC587BBCZ-5B

Overview

ADSP-SC587BBCZ-5B from Analog Devices is a dual-core SHARC+ and Arm Cortex-A5 heterogeneous processor for high-performance audio, automotive, and industrial signal processing. It integrates two 500 MHz SHARC+ floating-point DSP cores with 5 Mb L1 SRAM per core, a 500 MHz Arm Cortex-A5 core with 32 kB I/D cache and 256 kB L2 cache, and supports 32-/40-/64-bit floating-point arithmetic. Key peripherals include dual CAN 2.0 interfaces, dual USB 2.0 HS PHYs, PCIe 2.0 (1 lane), dual EMACs, and 8-channel 12-bit HADC - deployed in professional audio mixing consoles and ADAS domain controllers.

For engineers reviewing the ADSP-SC587BBCZ-5B datasheet, ADSP-SC587BBCZ-5B pinout, ADSP-SC587BBCZ-5B application, or ADSP-SC587BBCZ-5B equivalent, this page delivers verified architecture details, validated package mapping, confirmed peripheral integration (including PCIe, dual CAN, dual USB HS), and real-world timing and memory configuration constraints essential for automotive-grade BOM validation and multi-core firmware partitioning.

Technical Context

The ADSP-SC587BBCZ-5B implements a tightly coupled heterogeneous architecture: dual SHARC+ cores operate at 500 MHz each with independent 5 Mb L1 SRAM (configurable as SRAM or cache) and full IEEE 32/40/64-bit FP support, while the Arm Cortex-A5 runs at 500 MHz with NEON/VFPv4-D16, TrustZone security, and 256 kB parity-protected L2 cache. Both domains share a unified system fabric with coherency maintained via dual 64-bit requester/completer ports.

Memory subsystem includes 256 kB ECC-protected L2 SRAM, 512 kB L2 ROM, dual 16-bit DDR3/DDR2/LPDDR1 controllers, and asynchronous memory interface. Safety-critical features include dual CRC engines, watchdog timers, thermal monitor unit (TMU), and AEC-Q100 qualification - enabling use in ASIL-B–capable automotive control units without external safety monitors.

Key Specifications

Pinout & Package

ADSP-SC587BBCZ-5B uses a 529-ball CSP_BGA package (19 mm × 19 mm, 0.8 mm pitch), RoHS compliant, with ball assignments defined in Analog Devices' official ADSP-SC58x Designer Quick Reference (Rev. C, pp. 163–169). The package supports full peripheral routing including dual CAN, PCIe 2.0 (1 lane), dual USB 2.0 HS PHYs, and dual 10/100/1000 EMACs with IEEE 1588 timestamping.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP + application processor applications.

Compared with ADSP-SC589BBCZ-5B, ADSP-SC587BBCZ-5B omits RTC and SDIO but retains identical SHARC+ performance, PCIe root capability, and dual CAN - making it more cost-effective for USB-connected audio or CAN-based ADAS gateways. Versus i.MX 8M Plus, ADSP-SC587BBCZ-5B delivers 3× higher sustained FP throughput and hardware-verified sub-50 µs audio path jitter, critical for medical and professional audio certification.

Availability

ADSP-SC587BBCZ-5B is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, professional audio mixing consoles, industrial motor drives, and portable medical ultrasound systems requiring stable component supply across extended product lifecycles.

Supply support for ADSP-SC587BBCZ-5B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, headquartered in Wilmington, MA, with design centers worldwide and over 50 years of signal processing innovation.

The ADSP-SC587BBCZ-5B belongs to the SHARC+ family - engineered specifically for deterministic, high-precision floating-point computation in safety- and latency-critical systems such as automotive radar, pro audio, and industrial automation.

FAQ

What is the maximum operating frequency of each core in the ADSP-SC587BBCZ-5B?

The ADSP-SC587BBCZ-5B features two SHARC+ cores each rated at 500 MHz and one Arm Cortex-A5 core also rated at 500 MHz. These frequencies are guaranteed across the full automotive temperature range (−40°C to +105°C) per AEC-Q100 Grade 2 qualification. All three cores operate concurrently with independent clock domains managed by the on-chip clock generation unit (CGU), and the ADSP-SC587BBCZ-5B datasheet specifies timing margins for synchronous cross-domain handshaking at these speeds.

Does the ADSP-SC587BBCZ-5B support PCIe 2.0 in endpoint mode?

No, the ADSP-SC587BBCZ-5B supports PCIe 2.0 exclusively in root complex mode - it can initiate transactions and configure downstream devices but cannot operate as an endpoint (e.g., as a PCIe slave device). This is confirmed in the "Processor Peripherals" section of the ADSP-SC58x datasheet (Rev. C, p.15) and distinguishes it from the ADSP-SC589BBCZ-5B, which supports both root and endpoint modes. For endpoint use cases, ADSP-SC589BBCZ-5B or external PCIe switch solutions are required.

How is memory coherency maintained between the Arm Cortex-A5 and SHARC+ cores in the ADSP-SC587BBCZ-5B?

Memory coherency in the ADSP-SC587BBCZ-5B is enforced through hardware-managed cache coherency using the PL310 L2 cache controller, which provides two 64-bit completer ports - one connecting Arm Cortex-A5 instruction/data interfaces and another linking Arm and SHARC+ cores for data coherency. The system fabric ensures snoop-based coherency for shared L2 SRAM and peripheral register accesses, eliminating software cache maintenance overhead for inter-processor communication buffers.

What boot sources are supported by the ADSP-SC587BBCZ-5B, and how are they selected?

The ADSP-SC587BBCZ-5B supports boot from SPI flash, quad-SPI flash, SD/eMMC, and USB recovery mode - selected via strapping of BOOT_CFG[3:0] pins at power-up. Boot mode decoding is hardwired and does not require firmware intervention; the internal boot ROM validates image integrity using CRC before loading to L1 SRAM. This configuration is documented in Table 12 ("Boot Mode Selection") of the ADSP-SC58x Designer Quick Reference (Rev. C, p.62), and the ADSP-SC587BBCZ-5B implements identical boot logic as other SC58x variants.

Is the ADSP-SC587BBCZ-5B pin-compatible with other SC58x processors like the ADSP-SC584BBCZ-4?

No, the ADSP-SC587BBCZ-5B is not pin-compatible with ADSP-SC584BBCZ-4. The ADSP-SC587BBCZ-5B uses a 529-ball CSP_BGA package, whereas ADSP-SC584BBCZ-4 uses a 349-ball CSP_BGA package - differing in size (19 mm × 19 mm vs 19 mm × 19 mm but different ball layout), pitch (0.8 mm), and I/O count. Ball assignments, power rail distribution, and peripheral pin mappings differ significantly; PCB redesign is required when migrating between these packages, as confirmed in Analog Devices' "349-Ball vs 529-Ball CSP_BGA Configuration" guide (Rev. C, pp.162, 169).