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Analog Devices Inc. ADSP-SC592KBPZ10
- Part No.:
- ADSP-SC592KBPZ10
- Manufacturer:
- Analog Devices Inc.
- Category:
- DSP (Digital Signal Processors)
- Package:
- 400-FBGA
- Datasheet:
-
ADSP-SC592KBPZ10.pdf
- Description:
- 1GHz Cortex A5, 1GHz SHARC+
- Quantity:
- Payment:
- Shipping:
Inventory:3,217
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Product details
Overview
ADSP-SC592KBPZ10 from Analog Devices is a dual-core SHARC+ DSP with integrated Arm Cortex-A5 processor in a 400-ball BGA_ED package (17 mm × 17 mm, 0.8 mm pitch), delivering up to 1 GHz SHARC+ core frequency and 1 GHz Arm Cortex-A5 performance (1600 DMIPS). It features 5 Mb L1 SRAM per SHARC+ core with parity, 256 kB L2 cache with parity, and 2 MB shared L2 SRAM with ECC - optimized for high-fidelity audio processing, automotive ANC/RNC, and real-time signal conditioning in safety-critical systems.
For engineers reviewing the ADSP-SC592KBPZ10 datasheet, ADSP-SC592KBPZ10 pinout, ADSP-SC592KBPZ10 application, or ADSP-SC592KBPZ10 equivalent, key selection criteria include dual-core floating-point throughput (32/40/64-bit), on-chip memory partitioning (L1 SRAM vs cache), Arm TrustZone support, CAN FD interface availability, and AEC-Q100 qualification for automotive deployment.
Technical Context
The ADSP-SC592KBPZ10 integrates one SHARC+ core (1000 MHz) and one Arm Cortex-A5 core (1000 MHz), sharing a unified system fabric with L2 SRAM (2 MB, ECC-protected) and DDR3/DDR3L interface (16-bit). Its dual-core architecture enables heterogeneous task partitioning: SHARC+ handles deterministic, low-latency floating-point signal processing (e.g., FIR/IIR filtering at up to 1 GHz), while the Arm core manages OS services, connectivity, and high-level control.
Hardware acceleration includes dedicated FIR and IIR accelerators per SHARC+ core, cryptographic engine for secure boot, and system-level safety features including memory protection units (SMPU/SPU), fault management unit (FMU), and thermal monitor unit (TMU). The device supports Arm TrustZone, dual CRC with MemDMA, and AEC-Q100 Grade 2 qualification (−40°C to +105°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| SHARC+ Core Speed | 1000 MHz - enables real-time execution of 64-bit floating-point FFTs and adaptive filters without external memory bottlenecks. |
| Arm Cortex-A5 Speed | 1000 MHz / 1600 DMIPS - supports Linux RTOS, USB 2.0 HS OTG, and Ethernet AVB stack with NEON/VFPv4-D16 acceleration. |
| L1 SRAM per SHARC+ Core | 5 Mb (640 kB) with parity - configurable as SRAM or cache; provides zero-wait-state access for time-critical audio buffers and coefficient tables. |
| L2 Cache | 256 kB with parity - maintains coherency between Arm and SHARC+ cores via PL310 controller for shared data structures. |
| L2 SRAM | 2 MB with ECC - serves as shared scratchpad for inter-core messaging, ASRC buffer staging, and safety-critical data logging. |
| Peripheral Interface | 2× CAN FD, 2× EMAC (10/100/1000 Mbps with IEEE 1588), 8× full SPORTs, 2× S/PDIF, 8× ASRC pairs - supports multi-zone automotive audio routing and synchronized sensor fusion. |
| Package & Qualification | 400-ball BGA_ED (17 mm × 17 mm, 0.8 mm pitch), RoHS compliant, AEC-Q100 Grade 2 - validated for under-hood and cockpit deployment in ADAS and digital cockpit systems. |
Pinout & Package
ADSP-SC592KBPZ10 uses a 400-ball BGA_ED package (17 mm × 17 mm, 0.8 mm pitch), RoHS compliant, with ball assignments defined in Analog Devices' ADSP-21593/21594/ADSP-SC592/SC594 Rev. E documentation (pages 131–144). Pinout supports high-peripheral-count (HPC) configuration with 135 GPIO + 40 DAI pins, 2× CAN FD, 2× EMAC, 4× UARTs, 6× I²C, and dual 4-channel PDM microphone inputs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_INT | Core power supply | 1.0 V ±3% supply for SHARC+ and Arm cores; requires low-noise regulation and local decoupling for jitter-sensitive audio clocking. |
| VDD_IO | I/O power supply | 1.8 V or 3.3 V selectable per bank; supports mixed-voltage interfacing with ADCs, codecs, and automotive CAN transceivers. |
| CLKIN | System clock input | Differential or single-ended reference (1–50 MHz); feeds CGU for generating core clocks, ASRC clocks, and precision clock generators (PCGs). |
| BOOT_CFG[3:0] | Boot mode configuration | Strap pins determining boot source (SPI flash, QSPI, SD/MMC, or USB); critical for secure boot sequence and firmware authentication. |
| EMAC_RXD[3:0] | Ethernet MAC receive data | 4-bit nibble of RMII/MII interface; enables time-synchronized audio streaming over AVB networks with IEEE 1588 timestamping. |
| CANFD_TX0/CANFD_RX0 | CAN FD channel 0 differential pair | Supports 5 Mbps data phase; used for real-time vehicle bus communication in ANC/RNC control loops and head unit integration. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core heterogeneous compute | SHARC+ (1000 MHz) + Arm Cortex-A5 (1000 MHz) enables parallel execution of real-time DSP kernels and application-layer software without resource contention. |
| Floating-point precision flexibility | Native 32/40/64-bit IEEE floating-point + 32-bit fixed-point; allows trade-off between dynamic range (e.g., 120+ dB SNR in ANC) and memory footprint. |
| On-chip memory protection | SMPU and SPU enforce memory isolation between Arm OS, SHARC+ firmware, and safety-critical partitions - required for ISO 26262 ASIL-B compliance. |
| Hardware security acceleration | Cryptographic engine supports AES-128/256, SHA-256, RSA, and fast secure boot with OTP-based key storage - prevents firmware tampering in connected vehicles. |
| Automotive-grade peripherals | AEC-Q100 Grade 2 rating, CAN FD, ASRC, and PDM mic inputs enable direct integration into automotive audio ECUs without external signal conditioning. |
Applications
| Automotive Audio Amplifier | Active Noise Cancellation (ANC) |
|---|---|
Use Scenario: High-power Class-D amplifier in premium vehicle sound systems with real-time equalization and speaker protection. IC Role / Device Role / Timing Role: ADSP-SC592KBPZ10 performs multi-band parametric EQ, loudspeaker thermal modeling, and PWM modulation timing generation using its SHARC+ core and precision clock generators. Use Value: 5 Mb L1 SRAM enables storage of 128+ filter coefficients per channel; 64-bit floating-point ensures <0.001% THD+N across 20 Hz–20 kHz bandwidth. |
Use Scenario: Cabin-wide noise suppression using error microphone feedback and feedforward path adaptation in electric vehicles. IC Role / Device Role / Timing Role: ADSP-SC592KBPZ10 executes adaptive LMS/FXLMS algorithms on SHARC+ core while Arm core handles Bluetooth audio streaming and UI updates. Use Value: Dual FIR accelerators running at 1 GHz reduce convergence time to <5 ms; 2 MB L2 SRAM stores multiple acoustic models for different driving conditions. |
| Rear Seat Entertainment System | Digital Cockpit Audio Hub |
Use Scenario: Multi-zone audio decoding, spatial rendering, and HDMI/USB audio passthrough for rear passengers. IC Role / Device Role / Timing Role: ADSP-SC592KBPZ10 uses Arm Cortex-A5 for Linux-based media framework and SHARC+ for Dolby Atmos® decoding and head-related transfer function (HRTF) convolution. Use Value: 8× ASRC pairs enable sample-rate conversion between 44.1 kHz (CD), 48 kHz (USB), and 96 kHz (Blu-ray) sources with <±1 ppm jitter. |
Use Scenario: Centralized audio processing node aggregating voice assistant, navigation alerts, phone calls, and infotainment streams. IC Role / Device Role / Timing Role: ADSP-SC592KBPZ10 routes 16+ audio channels via DAI/SRU, applies beamforming on 2× 4-channel PDM inputs, and synchronizes playback using GIC-driven interrupt scheduling. Use Value: 135 GPIO + 40 DAI pins support simultaneous connection to 8+ microphones, 6+ speakers, and 3+ codecs; TMU monitors die temperature to throttle non-critical tasks during thermal stress. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core DSP + application processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADSP-SC594KBPZ10 | Higher peripheral count: adds ePPI, MLB 6-pin, USB 2.0 HS OTG, and 10/100/1000 EMAC with AVB; same SHARC+/Arm speeds and memory. | Required for designs needing parallel video capture (ePPI), high-speed USB device mode, or gigabit Ethernet AVB synchronization. | Select ADSP-SC594KBPZ10 when full HPC peripheral set is needed; ADSP-SC592KBPZ10 is optimal for cost-sensitive audio-only or CAN FD–focused automotive ECUs. |
| ADSP-21594KCPZ | Single SHARC+ core (1000 MHz), no Arm Cortex-A5; retains 2 MB L2 SRAM, 2× CAN FD, and ASRC but lacks TrustZone, L2 cache, and Linux-capable application core. | Suitable for pure DSP workloads (e.g., legacy audio amplifiers) where OS abstraction and secure boot are unnecessary. | Choose ADSP-21594KCPZ for deterministic, single-threaded DSP tasks; ADSP-SC592KBPZ10 is mandatory when concurrent OS services, secure firmware updates, or heterogeneous compute are required. |
Compared with ADSP-SC594KBPZ10, ADSP-SC592KBPZ10 reduces BOM cost and PCB complexity by omitting ePPI and USB OTG while retaining identical DSP performance and automotive qualification. Against ADSP-21594KCPZ, it adds Arm-based system management and security - essential for OTA-updatable, ISO 26262-compliant vehicle architectures.
Availability
ADSP-SC592KBPZ10 is available at Aetrix Electronics and suitable for automotive audio amplifier modules, active noise cancellation systems, and digital cockpit audio hubs requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.
Supply support for ADSP-SC592KBPZ10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and DSP technology, headquartered in Wilmington, MA, with design centers worldwide and a 50+ year heritage in precision signal processing.
The ADSP-SC592KBPZ10 belongs to Analog Devices' SHARC+ dual-core processor family, engineered specifically for automotive and professional audio applications demanding deterministic floating-point performance, functional safety, and hardware-enforced security in a single chip.
FAQ
What is the maximum operating temperature range for the ADSP-SC592KBPZ10?
The ADSP-SC592KBPZ10 is qualified to AEC-Q100 Grade 2, supporting operation from −40°C to +105°C ambient temperature. This rating is validated across all electrical specifications, including L1 SRAM retention, CAN FD timing, and thermal monitor unit (TMU) accuracy, making it suitable for under-dash and center-console automotive environments where thermal cycling is severe.
Does the ADSP-SC592KBPZ10 support secure boot with cryptographic verification?
Yes, the ADSP-SC592KBPZ10 includes a hardware cryptographic engine and one-time programmable (OTP) memory to implement fast secure boot. During power-on reset, the boot ROM validates firmware signatures using AES-256 and SHA-256 before loading code into L1 SRAM - preventing unauthorized firmware execution and ensuring IP protection for proprietary audio algorithms.
How many independent audio sample-rate converters does the ADSP-SC592KBPZ10 integrate?
The ADSP-SC592KBPZ10 integrates eight asynchronous sample-rate converters (ASRCs), organized as four pairs per DAI block. Each ASRC supports conversion ratios from 1:16 to 16:1 with <±1 ppm jitter and 120+ dB SNR, enabling seamless interoperability between disparate audio sources such as Bluetooth (48 kHz), CD (44.1 kHz), and high-res streaming (192 kHz) within a single ADSP-SC592KBPZ10-based system.
Is the ADSP-SC592KBPZ10 pin-compatible with other SHARC+ processors like the ADSP-21594?
No, the ADSP-SC592KBPZ10 is not pin-compatible with the ADSP-21594KCPZ. While both use the same 400-ball BGA_ED package footprint, their pin functions differ significantly: ADSP-SC592KBPZ10 includes Arm-specific signals (e.g., AXI bus, GIC interrupts) and dual-core interconnects absent in the single-core ADSP-21594, requiring unique PCB layout and power delivery design.
What development tools are officially supported for the ADSP-SC592KBPZ10?
Analog Devices provides CrossCore Embedded Studio (CCES) with SHARC+ and Arm Cortex-A5 debug support, ICE-1000/2000 emulators, and EZ-KIT evaluation boards (e.g., EVAL-SC592). The toolchain includes SHARC+ C/C++ compiler, Arm GCC toolset, VisualDSP++ legacy compatibility, and pre-verified drivers for CAN FD, ASRC, and PDM interfaces - all validated for ADSP-SC592KBPZ10 silicon revision and package variant.
ADSP-SC592KBPZ10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- SHARC®
- Package/Case:
- 400-FBGA
- Packaging:
- Tray
- Product Status:
- Active
- Type:
- Fixed/Floating Point
- Interface:
- CAN, DDR2, DDR3, EBI/EMI, Ethernet, DAI, I2C, SPI, SPORT, UART/USART, USB OTG
- Clock Rate:
- 1GHz DSP, 1GHz ARM®
- Non-Volatile Memory:
- External
- On-Chip RAM:
- 2.625MB
- Voltage - I/O:
- 3.30V
- Voltage - Core:
- 1V
- Operating Temperature:
- 0°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 400-BGA (17x17)
ADSP-SC592KBPZ10 FAQ
1.How can I place an order for ADSP-SC592KBPZ10 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADSP-SC592KBPZ10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADSP-SC592KBPZ10 reliable?
The price and inventory of ADSP-SC592KBPZ10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADSP-SC592KBPZ10 is usually 5 days.
3.What payment methods are accepted for ADSP-SC592KBPZ10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADSP-SC592KBPZ10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADSP-SC592KBPZ10?
ADSP-SC592KBPZ10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADSP-SC592KBPZ10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADSP-SC592KBPZ10?
For technical support, including ADSP-SC592KBPZ10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADSP-SC592KBPZ10 requirements.
6.How does Aetrix verify that ADSP-SC592KBPZ10 is sourced from the original manufacturer or authorized distributors?
All ADSP-SC592KBPZ10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADSP-SC592KBPZ10 meets industry standards.
7.What is the process for return or replacement of ADSP-SC592KBPZ10?
All ADSP-SC592KBPZ10 units undergo pre-shipment inspection (PSI). If there is an issue with ADSP-SC592KBPZ10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADSP-SC592KBPZ10 part is unused and in its original packaging.
Return procedure for ADSP-SC592KBPZ10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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