Analog Devices Inc. ADSP-SC598BBPZ10

Overview

ADSP-SC598BBPZ10 from Analog Devices is a dual-core heterogeneous processor integrating one Arm Cortex-A55 core (up to 1200 MHz) and two SHARC+ floating-point DSP cores (up to 1000 MHz and 812.5 MHz respectively), with 2 MB shared L2 SRAM (ECC), dual 256 kB L2 cache (ECC), and 5 Mb L1 SRAM per SHARC+ core (parity). It supports AEC-Q100 automotive qualification, CAN FD, dual EMAC (10/100/1000), and cryptographic acceleration - deployed in automotive ADAS audio preprocessing and real-time sensor fusion systems.

For engineers reviewing the ADSP-SC598BBPZ10 datasheet, ADSP-SC598BBPZ10 pinout, ADSP-SC598BBPZ10 application, or ADSP-SC598BBPZ10 equivalent, key selection criteria include dual-core clock asymmetry (1000/812.5 MHz SHARC+ pairing), 400-ball BGA_ED package compatibility, DDR3L interface timing, TrustZone-enabled secure boot, and FIR/IIR offload engine throughput at 1 GHz.

Technical Context

The ADSP-SC598BBPZ10 implements a tightly coupled heterogeneous architecture: the Arm Cortex-A55 core handles high-level OS tasks and multimedia middleware using AArch64 execution state, 32 kB L1 instruction cache (parity), 32 kB L1 data cache (ECC), and 256 kB unified L2 cache (ECC); concurrently, the dual SHARC+ cores execute deterministic floating-point signal processing via 5 Mb L1 SRAM per core, 32-/40-/64-bit IEEE float support, and zero-overhead circular buffer addressing.

System-level integration includes a shared 2 MB L2 SRAM with ECC, a 16-bit DDR3/DDR3L interface (L3), eight MemDMAs, Arm CoreSight debug infrastructure, and hardware accelerators for FIR (1 per SHARC+ core), IIR (4 per SHARC+ core), ASRC (8 pairs), and cryptographic operations (AES/SHA-256/Galois/Counter Mode).

Key Specifications

Pinout & Package

ADSP-SC598BBPZ10 uses a 400-ball BGA_ED package (17 mm × 17 mm, 0.8 mm pitch) with ball assignments defined in Analog Devices' ADSP-SC596/ADSP-SC598 Rev. B documentation (Pages 133–138). Pin functions are multiplexed across GPIO ports A–I (135 pins), DAI interfaces (40 pins), and dedicated peripheral balls including DDR3L, EMAC, CAN FD, USB, and clock/reset domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous DSP + application processor applications.

Compared with ADSP-SC596BBPZ10, the ADSP-SC598BBPZ10 delivers 2× SHARC+ compute density for parallel filter banks or split-domain processing; versus i.MX 8M Plus, it provides deterministic sub-microsecond interrupt latency and native SHARC assembly compatibility - essential for certified automotive audio stacks.

Availability

ADSP-SC598BBPZ10 is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, professional audio mixing consoles, industrial sensor fusion gateways, and medical ultrasound beamformers requiring stable component supply across extended product lifecycles.

Supply support for ADSP-SC598BBPZ10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, communications, and industrial systems.

The ADSP-SC598BBPZ10 belongs to Analog Devices' SHARC+ family - designed specifically for automotive and professional audio applications demanding deterministic floating-point performance, hardware-accelerated signal processing, and functional safety compliance.

FAQ

What is the maximum operating frequency of each core in the ADSP-SC598BBPZ10?

The ADSP-SC598BBPZ10 features an Arm Cortex-A55 core rated up to 1200 MHz and two SHARC+ cores operating at asymmetric frequencies: Core 1 up to 1000 MHz and Core 2 up to 812.5 MHz. These speed grades are validated under automotive temperature conditions (−40°C to +125°C) and specified in the ADSP-SC596/ADSP-SC598 Rev. B datasheet Table 1. The ADSP-SC598BBPZ10's dual SHARC+ configuration enables workload partitioning while maintaining instruction-set compatibility with prior SHARC processors.

Does the ADSP-SC598BBPZ10 support DDR3L memory, and what interface width is implemented?

Yes, the ADSP-SC598BBPZ10 integrates a 16-bit DDR3L memory controller via its L3 interface, supporting data rates up to 800 MT/s. This interface connects directly to external DDR3L SDRAM and is electrically compatible with standard DDR3L components. The ADSP-SC598BBPZ10's memory map reserves 0x60000000–0x7FFFFFFF for DDR3L address space, and timing parameters are fully specified in the "Timing Specifications" section (Page 71) of the Rev. B datasheet.

How many CAN FD interfaces does the ADSP-SC598BBPZ10 provide, and are they AEC-Q100 qualified?

The ADSP-SC598BBPZ10 includes two fully independent CAN FD controllers supporting data rates up to 5 Mbps, and both are AEC-Q100 Grade 2 qualified. These interfaces comply with ISO 11898-1:2015 and support protocol extensions including flexible data-rate arbitration and payload lengths up to 64 bytes. CAN FD functionality is enabled only on automotive-grade variants like the ADSP-SC598BBPZ10 - consumer-grade models omit this feature per the Ordering Guide (Page 141).

What cryptographic capabilities are integrated into the ADSP-SC598BBPZ10?

The ADSP-SC598BBPZ10 integrates a dedicated cryptographic hardware accelerator supporting AES-128/192/256 encryption/decryption, SHA-1/SHA-224/SHA-256 hashing, and Galois/Counter Mode (GCM) for authenticated encryption. It also implements Arm TrustZone security extensions and enables fast secure boot with one-time-programmable (OTP) key storage. These features are documented in the "Security Features" section (Page 14) and verified under AEC-Q100 stress testing for automotive deployment.

Is the ADSP-SC598BBPZ10 pin-compatible with other members of the ADSP-SC596/ADSP-SC598 family?

Yes, the ADSP-SC598BBPZ10 shares identical 400-ball BGA_ED packaging, pinout, and mechanical footprint with ADSP-SC596BBPZ10 and all other variants in the ADSP-SC596/ADSP-SC598 family. Ball assignments, power sequencing, and thermal pad layout are fully consistent across the family, enabling PCB reuse. However, functional differences exist - e.g., ADSP-SC598BBPZ10 enables dual SHARC+ cores while ADSP-SC596BBPZ10 implements only one - requiring firmware and memory map adjustments.